Chin-Long Wey

Personal Home Page

http://www.egr.msu.edu/~wey/research.html

Articles in Scholarly Journals [Incomplete List]

  1. International Journal of High Speed Electronics and Systems, vol. 14, no. 3, p. 825, 2004
  2. Design of fast high-radix SRT dividers and their VLSI implementation
    IEE Proceedings - Computers and Digital Techniques, vol. 147, no. 4, p. 275, 2000
  3. Analog Integrated Circuits and Signal Processing, vol. 23, no. 3, pp. 179–188, 2000
  4. A fully differential current copier for performance improvement
    International Journal of Circuit Theory and Applications, vol. 28, no. 2, pp. 101–108, 2000
  5. Redesignability check for analog circuits with incomplete implementation information
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 46, no. 8, pp. 939–949, 1999
  6. A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic A/D converter
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 5, pp. 507–516, 1999
  7. Design and analysis of high performance current reference generators for low-power CMOS data converters
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 5, pp. 647–652, 1999
  8. Efficient conversion algorithms for long-word-length binary logarithmic numbers and logic implementation
    IEE Proceedings - Computers and Digital Techniques, vol. 146, no. 6, p. 295, 1999
  9. Efficient algorithms for binary logarithmic conversion and addition
    IEE Proceedings - Computers and Digital Techniques, vol. 146, no. 3, p. 168, 1999
  10. Design of a fast radix-4 SRT divider and its VLSI implementation
    IEE Proceedings - Computers and Digital Techniques, vol. 146, no. 4, p. 205, 1999
  11. Diagnosability analysis of analogue circuits
    International Journal of Circuit Theory and Applications, vol. 26, no. 5, pp. 439–451, 1998
  12. Fault macromodel for switches in switched-current circuits
    International Journal of Circuit Theory and Applications, vol. 26, no. 1, pp. 93–102, 1998
  13. Design of a high-speed square generator
    IEEE Transactions on Computers, vol. 47, no. 9, pp. 1021–1026, 1998
  14. ATPRG: an automatic test program generator using HDL-A for fault diagnosis of analog/mixed-signal integrated circuits
    IEEE Transactions on Instrumentation and Measurement, vol. 47, no. 2, pp. 426–431, 1998
  15. A high-accuracy CMOS oversampling switched-current sample/hold (S/H) circuit using feedforward approach
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 3, pp. 395–399, 1998
  16. Built-in self-test design of current-mode algorithmic analog-to-digital converters
    IEEE Transactions on Instrumentation and Measurement, vol. 46, no. 3, pp. 667–671, 1997
  17. GRASS: An efficient gate re-assignment algorithm for inverter minimisation in post technology mapping
    IEE Proceedings - Computers and Digital Techniques, vol. 144, no. 5, p. 348, 1997
  18. Built-in self-test (BIST) design of high-speed carry-free dividers
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, no. 1, pp. 141–145, 1996
  19. Simple low-voltage high-speed high-linearity V-I converter with S/H for analog signal processing applications
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, no. 1, pp. 52–55, 1996
  20. Design of high-speed high-accuracy current copiers for low-voltage analog signal processing applications
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, no. 12, pp. 836–839, 1996
  21. Test generation and concurrent error detection in current-mode A/D converters
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 10, pp. 1291–1298, 1995
  22. Application of bipartite graphs for achieving race-free state assignments
    IEEE Transactions on Computers, vol. 44, no. 8, pp. 1002–1011, 1995
  23. Design and test generation of C-testable high-speed carry-free dividers
    IEE Proceedings - Computers and Digital Techniques, vol. 142, no. 3, p. 193, 1995
  24. SOLiT: An automated system for synthesising reliable sequential circuits with multilevel logic implementation
    IEE Proceedings - Computers and Digital Techniques, vol. 142, no. 1, p. 49, 1995
  25. Simple yet accurate current copiers for low-voltage current-mode signal-processing applications
    International Journal of Circuit Theory and Applications, vol. 23, no. 2, pp. 137–145, 1995
  26. Efficient modelling and synthesis procedure of asynchronous sequential logic elements
    IEE Proceedings - Computers and Digital Techniques, vol. 141, no. 1, p. 61, 1994
  27. Concurrent-error detection in high-speed carry-free dividers
    IEE Proceedings - Computers and Digital Techniques, vol. 141, no. 6, p. 356, 1994
  28. Design of concurrent error detectable current-mode A/D converters for real-time applications
    Analog Integrated Circuits and Signal Processing, vol. 4, no. 1, pp. 65–74, 1993
  29. An accurate reference-generating circuit for successive approximation current mode A/D converters
    International Journal of Circuit Theory and Applications, vol. 21, no. 4, pp. 361–369, 1993
  30. Current-mode divide-by-two circuit
    Electronics Letters, vol. 28, no. 9, p. 820, 1992
  31. Built-in self-test (BIST) structures for analog circuit fault diagnosis with current test data
    IEEE Transactions on Instrumentation and Measurement, vol. 41, no. 4, pp. 535–539, 1992
  32. Concurrent error detection in current-mode A/D convertors
    Electronics Letters, vol. 27, no. 25, p. 2370, 1991
  33. Alternative built-in self-test (BIST) structures for analogue circuit fault diagnosis
    Electronics Letters, vol. 27, no. 18, p. 1627, 1991
  34. Design of fault-diagnosable and repairable folded PLAs for yield enhancement
    IEEE Journal of Solid-State Circuits, vol. 26, no. 1, pp. 54–57, 1991
  35. Built-in self-test (BIST) structure for analog circuit fault diagnosis
    IEEE Transactions on Instrumentation and Measurement, vol. 39, no. 3, pp. 517–521, 1990
  36. Reply to comments on ?Fault prediction for analog circuits?
    Circuits Systems and Signal Processing, vol. 9, no. 4, pp. 503–503, 1990
  37. An efficient output phase assignment for PLA minimization
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 1, pp. 1–7, 1990
  38. Fault prediction process for large analogue circuit networks
    International Journal of Circuit Theory and Applications, vol. 17, no. 2, pp. 141–149, 1989
  39. Design of fault diagnosable and repairable PLA's
    IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1451–1454, 1989
  40. Parallel processing for analogue fault diagnosis
    International Journal of Circuit Theory and Applications, vol. 16, no. 3, pp. 303–316, 1988
  41. Fault prediction for analog circuits
    Circuits, Systems, and Signal Processing, vol. 7, no. 1, pp. 95–109, 1988
  42. On yield consideration for the design of redundant programmable logic arrays
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 4, pp. 528–535, 1988
  43. On the implementation of an analog ATPG: the nonlinear case
    IEEE Transactions on Instrumentation and Measurement, vol. 37, no. 2, pp. 252–258, 1988
  44. The design of concurrent error diagnosable systolic arrays for band matrix multiplications
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 1, pp. 21–37, 1988
  45. On a Novel Self-test Approach to Digital Testing
    The Computer Journal, vol. 30, no. 3, pp. 258–267, 1987
  46. Invited paper. Algorithms for functional testing of digital systems
    International Journal of Electronics, vol. 62, no. 5, pp. 707–732, 1987
  47. Design of testability for analogue fault diagnosis
    International Journal of Circuit Theory and Applications, vol. 15, no. 2, pp. 123–142, 1987
  48. On the design of a redundant programmable logic array (RPLA)
    IEEE Journal of Solid-State Circuits, vol. 22, no. 1, pp. 114–117, 1987