Pinaki Mazumder

Personal Home Page

http://www.eecs.umich.edu/~mazum

Articles in Scholarly Journals [Incomplete List]

  1. Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 325–344, 2007
  2. Efficient Modeling of Transmission Lines With Electromagnetic Wave Coupling by Using the Finite Difference Quadrature Method
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 12, pp. 1289–1302, 2007
  3. Modeling of Gate Current and Capacitance in Nanoscale-MOS Structures
    IEEE Transactions on Electron Devices, vol. 53, no. 12, pp. 2950–2957, 2006
  4. Gate current modeling of high-k stack nanoscale MOSFETs
    Solid-State Electronics, vol. 50, no. 9-10, pp. 1489–1494, 2006
  5. Performance Modeling of Resonant Tunneling-Based Random-Access Memories
    IEEE Transactions On Nanotechnology, vol. 4, no. 4, pp. 472–480, 2005
  6. On Circuit Techniques to Improve Noise Immunity of CMOS Dynamic Logic
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 910–925, 2004
  7. Noise-Tolerant Quantum MOS Circuits Using Resonant Tunneling Devices
    IEEE Transactions On Nanotechnology, vol. 3, no. 1, pp. 134–146, 2004
  8. Accurate crosstalk noise modeling for early signal integrity analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 5, pp. 627–634, 2003
  9. Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1068–1079, 2003
  10. Simultaneous switching noise analysis using application specific device modeling
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1146–1152, 2003
  11. Accurate modeling of lossy nonuniform transmission lines by using differential quadrature methods
    IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 10, pp. 2233–2246, 2002
  12. A physical design tool for built-in self-repairable RAMs
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 2, pp. 352–364, 2001
  13. Augmentation of SPICE for simulation of circuits containing resonant tunneling diodes
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, pp. 39–50, 2001
  14. On optimal tapering of FET chains in high-speed CMOS circuits
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 12, pp. 1099–1109, 2001
  15. Digital integrated circuit using integrated InAlAs/InGaAs/InP HEMTs and InAs/AlSb/GaSb RITDs
    Electronics Letters, vol. 37, no. 12, p. 758, 2001
  16. CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices
    IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 924–932, 2001
  17. Redundant arithmetic, algorithms and implementations
    Integration, the VLSI Journal, vol. 30, no. 1, pp. 13–53, 2000
  18. Journal of Electronic Testing, vol. 16, no. 4, pp. 389–395, 2000
  19. Noise margins of threshold logic gates containing resonant tunneling diodes
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 10, pp. 1080–1085, 2000
  20. Resonant tunneling diodes: models and properties
    Proceedings of the IEEE, vol. 86, no. 4, pp. 641–660, 1998
  21. Digital circuit applications of resonant tunneling devices
    Proceedings of the IEEE, vol. 86, no. 4, pp. 664–686, 1998
  22. FTROM: A Silicon Compiler for Fault-tolerant ROMs
    Integration, the VLSI Journal, vol. 26, no. 1-2, pp. 117–140, 1998
  23. Multiple-valued signed digit adder using negative differential resistance devices
    IEEE Transactions on Computers, vol. 47, no. 9, pp. 947–959, 1998
  24. Tunneling devices and applications in high functionality/speed digital circuits
    Solid-State Electronics, vol. 41, no. 10, pp. 1515–1524, 1997
  25. Generation of minimal vertex covers for row/column allocation in self-repairable arrays
    IEEE Transactions on Computers, vol. 45, no. 1, pp. 109–115, 1996
  26. Compact multiple-valued multiplexers using negative differential resistance devices
    IEEE Journal of Solid-State Circuits, vol. 31, no. 8, pp. 1151–1156, 1996
  27. CHiRPS: a general-area parallel multilayer routing system
    IEE Proceedings - Computers and Digital Techniques, vol. 142, no. 3, p. 208, 1995
  28. Ultrafast pipelined arithmetic using quantum electronic devices
    IEE Proceedings - Computers and Digital Techniques, vol. 141, no. 2, p. 104, 1994
  29. Genetic beam search for gate matrix layout
    IEE Proceedings - Computers and Digital Techniques, vol. 141, no. 2, p. 123, 1994
  30. Guest editor's introduction
    Journal of Electronic Testing, vol. 5, no. 4, pp. 319–320, 1994
  31. Technology and layout-related testing of static random-access memories
    Journal of Electronic Testing, vol. 5, no. 4, pp. 347–365, 1994
  32. A survey of DA techniques for PLD and FPGA based systems
    Integration, the VLSI Journal, vol. 17, no. 3, pp. 191–240, 1994
  33. Coprocessor design for multilayer surface-mounted PCB routing
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 1, pp. 31–45, 1993
  34. Design of a fault-tolerant three-dimensional dynamic random-access memory with on-chip error-correcting circuit
    IEEE Transactions on Computers, vol. 42, no. 12, pp. 1453–1468, 1993
  35. Restructuring of square processor arrays by built-in self-repair circuit
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 9, pp. 1255–1265, 1993
  36. Wolverines: standard cell placement on a network of workstations
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 9, pp. 1312–1326, 1993
  37. Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp. 1885–1896, 1993
  38. An on-chip ECC circuit for correcting soft errors in DRAMs with trench capacitors
    IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1623–1633, 1992
  39. An efficient design of embedded memories and their testability analysis using Markov chains
    Journal of Electronic Testing, vol. 3, no. 3, pp. 235–250, 1992
  40. Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome
    Integration, the VLSI Journal, vol. 12, no. 1, pp. 49–77, 1991
  41. Ultrafast pipelined adders using RTTs
    Electronics Letters, vol. 27, no. 10, p. 830, 1991
  42. Subnanosecond 32 bit multiplier using negative differential resistance devices
    Electronics Letters, vol. 27, no. 21, p. 1929, 1991
  43. Circuit behavior modeling and compact testing performance evaluation
    IEEE Journal of Solid-State Circuits, vol. 26, no. 1, pp. 62–66, 1991
  44. A reconfigurable parallel signature analyzer for concurrent error correction in DRAM
    IEEE Journal of Solid-State Circuits, vol. 25, no. 3, pp. 866–870, 1990
  45. A genetic approach to standard cell placement using meta-genetic parameter optimization
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 5, pp. 500–511, 1990
  46. A hexagonal array machine for multilayer wire routing
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 10, pp. 1096–1112, 1990
  47. A neural network design for circuit partitioning
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 12, pp. 1265–1271, 1990
  48. An efficient built-in self testing for random-access memory
    IEEE Transactions on Industrial Electronics, vol. 36, no. 2, pp. 246–253, 1989
  49. Parallel testing for pattern-sensitive faults in semiconductor random-access memories
    IEEE Transactions on Computers, vol. 38, no. 3, pp. 394–407, 1989
  50. A test methodology for electronic neural-network associative memory P. Mazumder, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109
    Neural Networks, vol. 1, p. 394, 1988
  51. Methodologies for testing embedded content addressable memories
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 1, pp. 11–20, 1988
  52. Parallel testing of parametric faults in a three-dimensional dynamic random-access memory
    IEEE Journal of Solid-State Circuits, vol. 23, no. 4, pp. 933–941, 1988
  53. Evaluation of On-Chip Static Interconnection Networks
    IEEE Transactions on Computers, vol. C-36, no. 3, pp. 365–369, 1987
  54. Planar decomposition for quadtree data structure
    Computer Vision, Graphics, and Image Processing, vol. 38, no. 3, pp. 258–274, 1987