Shuvra Bhattacharyya

Shuvra Bhattacharyya is a Professor in the Department of Electrical and Computer Engineering, University of Maryland at College Park. He holds a joint appointment at the University of Maryland Institute for Advanced Computer Studies (UMIACS). Dr. Bhattacharyya is coauthor or coeditor of four books and the author or coauthor of more than 100 refereed technical articles. His research interests include VLSI signal processing, embedded software, and hardware/software codesign. He received the B.S. degree from the University of Wisconsin at Madison, and the Ph.D. degree from the University of California at Berkeley. Dr. Bhattacharyya has held industrial positions as a Researcher at the Hitachi America Semiconductor Research Laboratory, San Jose, California, and Compiler Developer at Kuck & Associates, Champaign, Ill, USA.

Biography Updated on 23 September 2007

Personal Home Page

http://www.ece.umd.edu/~ssb/

Articles in Scholarly Journals [Incomplete List]

  1. Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation
    IEEE Transactions on Signal Processing, vol. 55, no. 6, pp. 3126–3138, 2007
  2. Embedded Digital Signal Processing Systems
    EURASIP Journal on Embedded Systems, vol. 2007, Article ID 27517, 1 pages, 2007
  3. Dataflow-Based Mapping of Computer Vision Algorithms onto FPGAs
    EURASIP Journal on Embedded Systems, vol. 2007, Article ID 49236, 12 pages, 2007
  4. Design Methods for DSP Systems
    EURASIP Journal on Applied Signal Processing, vol. 2006, Article ID 47817, 3 pages, 2006
  5. Contention-Conscious Transaction Ordering in Multiprocessor DSP Systems
    IEEE Transactions on Signal Processing, vol. 54, no. 2, pp. 556–569, 2006
  6. Efficient Techniques for Clustering and Scheduling onto Embedded Multiprocessors
    IEEE Transactions on Parallel and Distributed Systems, vol. 17, no. 7, pp. 667–680, 2006
  7. Analysis of Dataflow Programs with Interval-limited Data-rates
    The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 43, no. 2-3, pp. 247–258, 2006
  8. Guest Editorial
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 40, no. 1, pp. 5–6, 2005
  9. Modeling of Block-Based DSP Systems
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 40, no. 3, pp. 289–299, 2005
  10. Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors
    IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, pp. 99–112, 2005
  11. Hardware/software codesign for DSP (from the Guest Editor)
    IEEE Signal Processing Magazine, vol. 22, no. 3, pp. 11–12, 2005
  12. Systematic Integration of Parameterized Local Search Into Evolutionary Algorithms
    IEEE Transactions on Evolutionary Computation, vol. 8, no. 2, pp. 137–155, 2004
  13. The Hierarchical Timing Pair Model for Multirate DSP Applications
    IEEE Transactions on Signal Processing, vol. 52, no. 5, pp. 1209–1217, 2004
  14. Buffer merging---a powerful technique for reducing memory requirements of synchronous dataflow specifications
    ACM Transactions on Design Automation of Electronic Systems, vol. 9, no. 2, pp. 212–237, 2004
  15. The CBP Parameter: A Module Characterization Approach for DSP Software Optimization
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 38, no. 2, pp. 131–146, 2004
  16. Editorial
    EURASIP Journal on Applied Signal Processing, vol. 2003, no. 6, pp. 491–493, 2003
  17. Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems
    EURASIP Journal on Applied Signal Processing, vol. 2003, no. 6, pp. 565–579, 2003
  18. Taking on the embedded system design challenge
    Computer, vol. 36, no. 4, pp. 35–37, 2003
  19. High-Level Synthesis of DSP Applications Using Adaptive Negative Cycle Detection
    EURASIP Journal on Applied Signal Processing, vol. 2002, no. 9, pp. 893–907, 2002
  20. Design Automation for Embedded Systems, vol. 7, no. 4, pp. 307–323, 2002
  21. Parameterized dataflow modeling for DSP systems
    IEEE Transactions on Signal Processing, vol. 49, no. 10, pp. 2408–2421, 2001
  22. Shared buffer implementations of signal processing systems using lifetime analysis techniques
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 177–198, 2001
  23. Resynchronization for multiprocessor DSP systems
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 47, no. 11, pp. 1597–1609, 2000
  24. Software synthesis and code generation for signal processing systems
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 9, pp. 849–875, 2000
  25. Evolutionary algorithms for the synthesis of embedded software
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 4, pp. 452–455, 2000
  26. The Journal of VLSI Signal Processing, vol. 24, no. 1, pp. 83–98, 2000
  27. The Journal of VLSI Signal Processing, vol. 21, no. 2, pp. 151–166, 1999
  28. Formal Methods in System Design, vol. 11, no. 1, pp. 41–70, 1997
  29. Design Automation for Embedded Systems, vol. 2, no. 1, pp. 33–60, 1997
  30. Optimizing synchronization in multiprocessor DSP systems
    IEEE Transactions on Signal Processing, vol. 45, no. 6, pp. 1605–1618, 1997
  31. Generating compact code from dataflow specifications of multirate signal processing algorithms
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 42, no. 3, pp. 138–150, 1995
  32. Memory management for dataflow programming of multirate signal processing algorithms
    IEEE Transactions on Signal Processing, vol. 42, no. 5, pp. 1190–1201, 1994
  33. Looped schedules for dataflow descriptions of multirate signal processing algorithms
    Formal Methods in System Design, vol. 5, no. 3, pp. 183–205, 1994
  34. Scheduling synchronous dataflow graphs for efficient looping
    Journal of VLSI Signal Processing, vol. 6, no. 3, pp. 271–288, 1993
  35. Gabriel: a design environment for DSP
    IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 37, no. 11, pp. 1751–1762, 1989