Leonel Sousa

Leonel Sousa received the Ph.D. degree in electrical and computers engineering from Instituto Superior Técnico (IST), Technical University of Lisbon, Portugal, in 1996. He is currently an Associate Professor of the Electrical and Computer Engineering Department at IST and a Senior Researcher of Instituto de Engenharia de Sistemas e Computadores-R&D (INESC-ID). His research interests include VLSI architectures, computer architectures, parallel and distributed computing, and multimedia systems. He has contributed to more than 150 papers to journals and international conferences and he is author of several book chapters. He has served in the program committee of numerous international conferences, he is Associate Editor of the EURASIP Journal on Embedded Systems, and he is currently a member of HiPEAC European Network of Excellence. He is a Senior Member of IEEE and a Member of ACM.

Biography Updated on 21 January 2008

Personal Home Page

http://medusa.inesc-id.pt/las/

Articles in Scholarly Journals [Incomplete List]

  1. Reconfigurable architectures and processors for real-time video motion estimation
    Journal of Real-Time Image Processing, vol. 2, no. 4, pp. 191–205, 2007
  2. Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures
    IET Computers & Digital Techniques, vol. 1, no. 5, p. 472, 2007
  3. Caravela: A Novel Stream-Based Distributed Computing Environment
    Computer, vol. 40, no. 5, pp. 70–77, 2007
  4. Adaptive Motion Estimation Processor for Autonomous Video Devices
    EURASIP Journal on Embedded Systems, vol. 2007, Article ID 57234, 10 pages, 2007
  5. Efficient Hybrid DCT-Domain Algorithm for Video Spatial Downscaling
    EURASIP Journal on Advances in Signal Processing, vol. 2007, Article ID 57291, 16 pages, 2007
  6. Embedded Systems for Portable and Mobile Video Platforms
    EURASIP Journal on Embedded Systems, vol. 2007, Article ID 63250, 2 pages, 2007
  7. A New Hand-Held Microsystem Architecture for Biological Analysis
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 11, pp. 2384–2395, 2006
  8. Toward a realistic task scheduling model
    IEEE Transactions on Parallel and Distributed Systems, vol. 17, no. 3, pp. 263–275, 2006
  9. A universal architecture for designing efficient modulo 2/sup n/+1 multipliers
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 6, pp. 1166–1178, 2005
  10. Corrections to “A Universal Architecture for Designing Efficient Modulo$2^n+1$Multipliers”
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 9, pp. 1982–1982, 2005
  11. Visual neuroprosthesis: a non invasive system for stimulating the cortex
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 12, pp. 2648–2662, 2005
  12. Communication contention in task scheduling
    IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 6, pp. 503–515, 2005
  13. On Task Scheduling Accuracy: Evaluation Methodology and Results
    The Journal of Supercomputing, vol. 27, no. 2, pp. 177–194, 2004
  14. List scheduling: extension for contention awareness and evaluation of node priorities for heterogeneous cluster architectures
    Parallel Computing, vol. 30, no. 1, pp. 81–101, 2004
  15. Fast transcoding architectures for insertion of non-regular shaped objects in the compressed DCT-domain
    Signal Processing: Image Communication, vol. 18, no. 8, pp. 659–683, 2003
  16. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 34, no. 3, pp. 277–290, 2003
  17. Algorithm for modulo (2n+1) multiplication
    Electronics Letters, vol. 39, no. 9, p. 752, 2003
  18. Efficient and configurable full-search block-matching processors
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 12, no. 12, pp. 1160–1167, 2002
  19. General method for eliminating redundant computations in video coding
    Electronics Letters, vol. 36, no. 4, p. 306, 2000