Scott Hauck

Scott Hauck received the B.S. degree in computer science from the University of California, Berkeley, in 1990, and the M.S. and Ph.D. degrees from the Department of Computer Science, University of Washington, Seattle, in 1992 and 1995, respectively. He is an Associate Professor of electrical engineering at the University of Washington. From 1995 to 1999, he was an Assistant Professor at Northwestern University. His research concentrates on FPGAs, including architectures, applications, and CAD tools, reconfigurable computing, and FPGA-based encryption and image compression. He has received a National Science Foundation (NSF) Career Award, a Sloan Fellowship, and a TVLSI Best Paper Award. He is a Senior Member of the IEEE.

Biography Updated on 13 July 2006

Personal Home Page

http://www.ee.washington.edu/people/faculty/hauck/

Articles in Scholarly Journals [Incomplete List]

  1. Automatic Design of Area-Efficient Configurable ASIC Cores
    IEEE Transactions on Computers, vol. 56, no. 5, pp. 662–672, 2007
  2. Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 291–295, 2007
  3. PipeRoute: A Pipelining-Aware Router for Reconfigurable Architectures
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 3, pp. 518–532, 2006
  4. Field-Programmable Gate Arrays in Embedded Systems
    EURASIP Journal on Embedded Systems, vol. 2006, Article ID 51312, 2 pages, 2006
  5. Précis: A Usercentric Word-Length Optimization Tool
    IEEE Design and Test of Computers, vol. 22, no. 4, pp. 349–361, 2005
  6. Resource Allocation for Coarse-Grain FPGA Development
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 10, pp. 1572–1581, 2005
  7. SPIHT Image Compression on FPGAs
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 9, pp. 1138–1147, 2005
  8. The Chimaera Reconfigurable Functional Unit
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 206–217, 2004
  9. Configuration relocation and defragmentation for run-time reconfigurable computing
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 3, pp. 209–220, 2002
  10. Reconfigurable computing: a survey of systems and software
    ACM Computing Surveys, vol. 34, no. 2, pp. 171–210, 2002
  11. High-performance carry chains for FPGA's
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 2, pp. 138–147, 2000
  12. Configuration compression for the Xilinx XC6200 FPGA
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 8, pp. 1107–1113, 1999
  13. Evaluation and optimization of replication algorithms for logic bipartitioning
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 9, pp. 1237–1248, 1999
  14. Mesh routing topologies for multi-FPGA systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 3, pp. 400–408, 1998
  15. The roles of FPGAs in reprogrammable systems
    Proceedings of the IEEE, vol. 86, no. 4, pp. 615–638, 1998
  16. An evaluation of bipartitioning techniques
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 8, pp. 849–866, 1997
  17. Pin assignment for multi-FPGA systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 9, pp. 956–964, 1997
  18. Asynchronous design methodologies: an overview
    Proceedings of the IEEE, vol. 83, no. 1, pp. 69–93, 1995
  19. Placement and routing tools for the Triptych FPGA
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, no. 4, pp. 473–482, 1995
  20. The Triptych FPGA architecture
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, no. 4, pp. 491–501, 1995