Antonio Nunez

Antonio Núñez was born in Madrid, Spain, in 1951. He received the Higher Engineering degree in 1974 from the School of Telecommunication Engineering at the Technical University of Madrid, and received the Ph.D. degree in 1981 from the same university. From 1974 to 1976 he worked as a Consultant for Telefonica. He was a Research Scientist with the Electrical Engineering Department of EPFL Lausanne, Switzerland, in 1981, working on CMOS processor design, and a Visiting Scientist (1986-1987) and a Visiting Professor (1987- 1988) at the School of Electrical Engineering of Purdue University, USA, working on compound-semiconductor high-speed VLSI design. He was appointed a Titular Professor at the University of Las Palmas de Gran Canaria, in 1982, and Professor in 1989. Among other academic positions he has served as a Director of the Department of Electronics, Director of the Institute for Applied Microelectronics, and Dean of the School of Telecommunication Engineering of ULPGC. He has published five books, over 40 journal papers, and 90 conference papers. He has supervised 11 Ph.D. theses. His current research fields include heterogeneous architecture platform-based design for embedded systems, communication architecture synthesis for MPSoC, multimedia processor architectures, DVB, DAB, and DMB codec design, and optimization of integrated circuits. He is a Member of IEEE Circuits and Systems Society, IEEE Standards Association (Design Languages), The European Association for Design Automation, Euromicro, and others.

Biography Updated on 8 July 2005

Articles in Scholarly Journals [Incomplete List]

  1. Embedded Systems for Portable and Mobile Video Platforms
    EURASIP Journal on Embedded Systems, vol. 2007, Article ID 63250, 2 pages, 2007
  2. Low-Cost Super-Resolution Algorithms Implementation Over a HW/SW Video Compression Platform
    EURASIP Journal on Applied Signal Processing, vol. 2006, Article ID 84614, 29 pages, 2006
  3. Advances in video coding for hand-held device implementation in networked electronic media
    Journal of Real-Time Image Processing, vol. 1, no. 1, pp. 9–23, 2006
  4. Characterization of extrinsic resistances in temperature behaviour modelling of InGaAs MODFETs
    Semiconductor Science and Technology, vol. 19, no. 5, pp. 648–654, 2004
  5. A scalable single-chip multi-processor architecture with on-chip RTOS kernel
    Journal of Systems Architecture, vol. 49, no. 12-15, pp. 619–639, 2003
  6. Analog Integrated Circuits and Signal Processing, vol. 35, no. 2/3, pp. 121–132, 2003
  7. Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp. 171–178, 2002
  8. Power model for DCFL family
    Electronics Letters, vol. 38, no. 1, p. 13, 2002
  9. Static simulation of pseudomorphic heterostructure FETs at medium/high temperatures
    Semiconductor Science and Technology, vol. 17, no. 6, pp. 534–539, 2002
  10. Quantitative study of the impact of design and synthesis options on processor core performance
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 3, pp. 461–473, 2001
  11. Semiconductor Science and Technology, vol. 15, no. 4, pp. L19–L23, 2000
  12. A CORDIC processor for FFT computation and its implementation using gallium arsenide technology
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 1, pp. 18–30, 1998
  13. Pipelined GaAs carry lookahead adder
    Electronics Letters, vol. 34, no. 18, p. 1732, 1998
  14. Noise margin enhancement in GaAs ROM's using current mode logic
    IEEE Journal of Solid-State Circuits, vol. 32, no. 4, pp. 592–597, 1997
  15. GaAs pseudodynamic latched logic for high performance processor cores
    IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1297–1303, 1997
  16. Gallium arsenide pseudo-dynamic latched logic
    Electronics Letters, vol. 32, no. 15, p. 1353, 1996
  17. An empirical model to estimate power consumption in GaAs DCFL/SDCFL circuits
    Microprocessing and Microprogramming, vol. 37, no. 1-5, pp. 23–26, 1993
  18. Integer and control units for a GaAs 32-bit RISC processor
    Microprocessing and Microprogramming, vol. 37, no. 1-5, pp. 105–108, 1993
  19. Multiobjective optimization using analytical models of GaAs high-speed digital circuits
    Microprocessing and Microprogramming, vol. 39, no. 2-5, pp. 267–270, 1993
  20. Timing analysis for DCFL/SDCFL VLSI circuits
    Microprocessing and Microprogramming, vol. 38, no. 1-5, pp. 511–518, 1993
  21. Timimg model for SDCFL digital circuits
    Microprocessing and Microprogramming, vol. 34, no. 1-5, pp. 193–196, 1992
  22. Accurate extraction of interconnect capacitances by adaptive mixed F.E.M.
    Microprocessing and Microprogramming, vol. 32, no. 1-5, pp. 61–68, 1991
  23. Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation
    Microprocessing and Microprogramming, vol. 32, no. 1-5, pp. 75–82, 1991
  24. MVM: A GaAs microprocessor for critical real-time applications
    Microprocessing and Microprogramming, vol. 27, no. 1-5, pp. 289–298, 1989
  25. Some results in GaAs processor design using LSI integrated circuits
    Microprocessing and Microprogramming, vol. 25, no. 1-5, pp. 127–132, 1989
  26. A survey of GaAs computer designs
    Microprocessing and Microprogramming, vol. 21, no. 1-5, pp. 665–670, 1987