Articles in Scholarly Journals [Incomplete List]

1. Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs
   Journal of Electronic Testing, vol. 23, no. 1, pp. 47–54, 2007
2. Efficient Techniques for Automatic Verification-Oriented Test Set Optimization
   International Journal of Parallel Programming, vol. 34, no. 1, pp. 93–109, 2006
3. Early, Accurate Dependability Analysis of CAN-Based Networked Systems
   IEEE Design and Test of Computers, vol. 23, no. 1, pp. 38–45, 2006
4. System-in-Package Testing: Problems and Solutions
   IEEE Design and Test of Computers, vol. 23, no. 3, pp. 203–211, 2006
5. A new hybrid fault detection technique for systems-on-a-chip
   IEEE Transactions on Computers, vol. 55, no. 2, pp. 185–198, 2006
6. Efficient analysis of single event transients
   Journal of Systems Architecture, vol. 50, no. 5, pp. 239–246, 2004
7. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
   Journal of Electronic Testing, vol. 20, no. 1, pp. 79–87, 2004
8. Code Generation for Functional Validation of Pipelined Microprocessors
   Journal of Electronic Testing, vol. 20, no. 3, pp. 269–278, 2004
9. A New Approach to Software-Implemented Fault Tolerance
   Journal of Electronic Testing, vol. 20, no. 4, pp. 433–437, 2004
10. A New Approach to the Analysis of Single Event Transients in VLSI Circuits
    Journal of Electronic Testing, vol. 20, no. 5, pp. 511–521, 2004
11. Automatic test program generation: a case study
    IEEE Design & Test of Computers, vol. 21, no. 2, pp. 102–109, 2004
12. Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs”
    IEEE Transactions on Nuclear Science, vol. 51, no. 2, pp. 328–328, 2004
13. Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
    IEEE Transactions on Nuclear Science, vol. 51, no. 6, pp. 3354–3359, 2004
14. Identification and classification of single-event upsets in the configuration memory of sram-based fpgas
    IEEE Transactions on Nuclear Science, vol. 50, no. 6, pp. 2088–2094, 2003
15. Impact of data cache memory on the single event upset-induced error rate of microprocessors
    IEEE Transactions on Nuclear Science, vol. 50, no. 6, pp. 2101–2106, 2003
16. New techniques for efficiently assessing reliability of SOCs
    Microelectronics Journal, vol. 34, no. 1, pp. 53–61, 2003
17. Journal of Electronic Testing, vol. 19, no. 5, pp. 499–499, 2003
18. Journal of Electronic Testing, vol. 19, no. 5, pp. 577–584, 2003
19. Journal of Electronic Testing, vol. 18, no. 3, pp. 261–271, 2002
20. Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study
    IEEE Transactions on Nuclear Science, vol. 49, no. 3, pp. 1491–1495, 2002
21. Initializability analysis of synchronous sequential circuits
    ACM Transactions on Design Automation of Electronic Systems, vol. 7, no. 2, pp. 249–264, 2002
22. Exploiting circuit emulation for fast hardness evaluation
    IEEE Transactions on Nuclear Science, vol. 48, no. 6, pp. 2210–2216, 2001
23. Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors
    IEEE Transactions on Nuclear Science, vol. 47, no. 6, pp. 2231–2236, 2000
24. SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 2, pp. 191–202, 1999
25. Integrating online and offline testing of a switching memory
    IEEE Design & Test of Computers, vol. 15, no. 1, pp. 63–70, 1998
26. Formal Methods in System Design, vol. 12, no. 3, pp. 267–289, 1998
27. EXFI: a low-cost fault injection system for embedded microprocessor-based boards
    ACM Transactions on Design Automation of Electronic Systems, vol. 3, no. 4, pp. 626–634, 1998
28. Circular self-test path for FSMs
    IEEE Design & Test of Computers, vol. 13, no. 4, pp. 50–60, 1996
29. GALLO: a genetic algorithm for floorplan area optimization
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 8, pp. 943–951, 1996
30. Industrial BIST of embedded RAMs
    IEEE Design and Test of Computers, vol. 12, no. 3, p. 86, 1995
31. A parallel system for test pattern generation
    Parallel Computing, vol. 19, no. 2, pp. 177–185, 1993
32. An approach to sequential circuit diagnosis based on formal verification techniques
    Journal of Electronic Testing, vol. 4, no. 1, pp. 11–17, 1993
33. TPDL: Extended temporal profile description language
    Software: Practice and Experience, vol. 21, no. 4, pp. 355–374, 1991
34. Exact probabilistic testability measures for multi-output circuits
    Journal of Electronic Testing, vol. 1, no. 3, pp. 229–234, 1990
35. Assessing the diagnostic power of test pattern sets
    Microprocessing and Microprogramming, vol. 30, no. 1-5, pp. 413–419, 1990
36. A transputer-based gate-level fault simulator
    Microprocessing and Microprogramming, vol. 30, no. 1-5, pp. 529–534, 1990
37. Expressing logical and temporal conditions in simulation environments: TPDL*
    Microprocessing and Microprogramming, vol. 26, no. 4, pp. 241–252, 1989