Vassilios A. Chouliaras0000-0003-0803-4689
Dr. Vassilios is a senior lecturer in microelectronics and embedded CPU architecture in the Electronic Systems Design Group, Systems Division. He conducts research in CPU architecture, Microarchitecture, ESL methodologies and software parallelization. He has been active in the design and implementation of scalar, superscalar and vector embedded microprocessors for over 14 years. Prior to his appointment at Loughborough University in 2002, he was a Senior R&D Engineer/Microprocessor architect for ARC International, working on various hardware projects in the embedded CPU architecture and microarchitectures domains. Prior to ARC, he worked as an ASIC design engineer for Intracom S.A. Prior to Intracom, he developed a 32-bit, 5-stage soft-IP CPU core, compliant with the MIPS-I ISA as the primary product of a private company. He has more than 80 publications in academic journals and international conferences, 5 international patent applications and was the Principal Investigator on an EPSRC-funded project [GR/S44976/01], which researched novel CPU architectures for acceleration of speech coding. He is a founder of Axilica Ltd and the Loughborough PI in the FP7 ENOSYS project.
Biography Updated on 23 June 2013