Spyros Tragoudas

Personal Home Page

http://www.engr.siu.edu/elec/faculty/tragoudas/tragoudas2.htm

Articles in Scholarly Journals [Incomplete List]

  1. Managing the power resources of sensor networks with performance considerations
    Computer Communications, vol. 30, no. 5, pp. 1122–1135, 2007
  2. High-Quality Transition Fault ATPG for Small Delay Defects
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 5, pp. 983–989, 2007
  3. Speedups in embedded systems with a high-performance coprocessor datapath
    ACM Transactions on Design Automation of Electronic Systems, vol. 12, no. 3, pp. 35–es, 2007
  4. Implicit grading of multiple path delay faults
    ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 2, pp. 346–361, 2006
  5. A High-Performance Data Path for Synthesizing DSP Kernels
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 6, pp. 1154–1163, 2006
  6. Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2954–2964, 2006
  7. Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 3026–3035, 2006
  8. InTeRail: a test architecture for core-based SOCs
    IEEE Transactions on Computers, vol. 55, no. 2, pp. 137–149, 2006
  9. Function-Based Compact Test Pattern Generation for Path Delay Faults
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 996–1001, 2005
  10. Efficient Identification of (Critical) Testable Path Delay Faults Using Decision Diagrams
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, pp. 77–87, 2005
  11. On-Chip Embedding Mechanisms for Large Sets of Vectors for Delay Test
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 488–497, 2005
  12. Rewiring for Watermarking Digital Circuit Netlists
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 7, pp. 1132–1137, 2005
  13. Journal of Circuits, Systems, and Computers, vol. 14, no. 4, p. 877, 2005
  14. Implicit Deductive Fault Simulation for Complex Delay Fault Models
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 6, pp. 636–641, 2004
  15. A Unified Framework for Generating All Propagation Functions for Logic Errors and Events
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 6, pp. 980–986, 2004
  16. Exact path delay fault coverage with fundamental zbdd operations
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 3, pp. 305–316, 2003
  17. An implicit path-delay fault diagnosis methodology
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1399–1408, 2003
  18. Journal of Electronic Testing, vol. 19, no. 3, pp. 233–244, 2003
  19. Path delay fault testing using test points
    ACM Transactions on Design Automation of Electronic Systems, vol. 8, no. 1, pp. 1–10, 2003
  20. ATPG tools for delay faults at the functional level
    ACM Transactions on Design Automation of Electronic Systems, vol. 7, no. 1, pp. 33–57, 2002
  21. An efficient algorithm for finding a path subject to two additive constraints
    Computer Communications, vol. 25, no. 3, pp. 225–238, 2002
  22. Journal of Electronic Testing, vol. 18, no. 3, pp. 305–313, 2002
  23. A new built-in TPG method for circuits with random pattern resistant faults
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 859–866, 2002
  24. On the nonenumerative path delay fault simulation problem
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 9, pp. 1095–1101, 2002
  25. Computational analysis of counter-based schemes for VLSI test pattern generation
    Discrete Applied Mathematics, vol. 110, no. 2-3, pp. 227–250, 2001
  26. The most reliable data-path transmission
    IEEE Transactions on Reliability, vol. 50, no. 3, pp. 281–285, 2001
  27. Von Neumann hybrid cellular automata for generating deterministic test sequences
    ACM Transactions on Design Automation of Electronic Systems, vol. 6, no. 3, pp. 308–321, 2001
  28. An efficient algorithm for finding a path subject to two additive constraints
    ACM SIGMETRICS Performance Evaluation Review, vol. 28, no. 1, pp. 318–327, 2000
  29. Test-set partitioning for multi-weighted random LFSRs
    Integration, the VLSI Journal, vol. 30, no. 1, pp. 65–75, 2000
  30. Transmissions in a network with capacities and delays
    Networks, vol. 33, no. 3, pp. 167–174, 1999
  31. Maximum weighted independent sets on transitive graphs and applications
    Integration, the VLSI Journal, vol. 27, no. 1, pp. 77–86, 1999
  32. On the design of optimal counter-based schemes for test set embedding
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 2, pp. 219–230, 1999
  33. A fast nonenumerative automatic test pattern generator for path delay faults
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 7, pp. 1050–1057, 1999
  34. Board-level partitioning for partial scan using fuzzy logic
    IEEE Transactions on Fuzzy Systems, vol. 7, no. 2, pp. 241–249, 1999
  35. Timing-Driven Circuit Implementation
    VLSI Design, vol. 7, no. 2, pp. 211–224, 1998
  36. Clustering Network Modules with Different Implementations for Delay Minimization
    VLSI Design, vol. 7, no. 1, pp. 1–13, 1998
  37. Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 3, pp. 309–315, 1997
  38. Implementing and clustering modules with complex delays
    Integration, the VLSI Journal, vol. 22, no. 1-2, pp. 39–57, 1997
  39. Improved approximations for the minimum-cut ratio and the flux
    Mathematical Systems Theory, vol. 29, no. 2, pp. 157–167, 1996
  40. Retiming-based partial scan
    IEEE Transactions on Computers, vol. 45, no. 1, pp. 74–87, 1996
  41. Min-cut partitioning on underlying tree and graph structures
    IEEE Transactions on Computers, vol. 45, no. 4, pp. 470–474, 1996
  42. On the use of counters for reproducing deterministic test sets
    IEEE Transactions on Computers, vol. 45, no. 12, pp. 1405–1419, 1996
  43. A fast algorithm for minimizing FPGA combinational and sequential modules
    ACM Transactions on Design Automation of Electronic Systems, vol. 1, no. 3, pp. 341–351, 1996
  44. Fast Approximation Algorithms for Multicommodity Flow Problems
    Journal of Computer and System Sciences, vol. 50, no. 2, pp. 228–243, 1995
  45. Avoiding linear dependencies in LFSR test pattern generators
    Journal of Electronic Testing, vol. 6, no. 2, pp. 229–241, 1995
  46. Pseudo-exhaustive built-in TPG for sequential circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 9, pp. 1160–1171, 1995
  47. A method for pseudo-exhaustive test pattern generation
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 9, pp. 1170–1178, 1994
  48. On Channel Routing Problems With Interchangeable Terminals
    VLSI Design, vol. 2, no. 1, pp. 51–68, 1994
  49. River routing and density minimization for channels with interchangeable terminals
    Integration, the VLSI Journal, vol. 15, no. 2, pp. 151–178, 1993
  50. Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 4, pp. 526–536, 1993
  51. A comparative study of five language independent programming environments
    Journal of Systems and Software, vol. 14, no. 1, pp. 3–15, 1991