Articles in Scholarly Journals [Incomplete List]

1. A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration
   The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 47, no. 3, pp. 297–315, 2007
2. On the Use of Model Checking for the Verification of a Dynamic Signature Monitoring Approach
   IEEE Transactions on Nuclear Science, vol. 52, no. 5, pp. 1555–1561, 2005
3. Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques
   ACM Transactions on Design Automation of Electronic Systems, vol. 10, no. 2, pp. 187–204, 2005
4. Computation of signal output probability for Boolean functions represented by OBDD
   Computers & Mathematics with Applications, vol. 47, no. 12, pp. 1865–1874, 2004
5. Electrical Field Analysis of Nanoscale Field Effect Transistors
   Japanese Journal of Applied Physics, vol. 43, no. No. 6B, pp. 3831–3837, 2004
6. Improvement of sensor accuracy in the case of a variable surface reflectance gradient for active laser range finders
   IEEE Transactions on Instrumentation and Measurement, vol. 52, no. 6, pp. 1799–1808, 2003
7. Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 3, pp. 346–351, 2003
8. An economic parallel processing technology for faster than real-time transient stability simulation
   European Transactions on Electrical Power, vol. 13, no. 2, pp. 105–112, 2003
9. A direct digital period synthesis circuit
   IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 1039–1045, 2002
10. A practical approach to model long MIS interconnects in VLSI circuits
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 4, pp. 494–507, 2002
11. Optimal design of synchronous circuits using software pipelining techniques
    ACM Transactions on Design Automation of Electronic Systems, vol. 6, no. 4, pp. 516–532, 2001
12. Direct digital frequency synthesis of low-jitter clocks
    IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 570–572, 2001
13. Implantable measurement technique dedicated to the monitoring of electrode-nerve contact in bladder stimulators
    Medical & Biological Engineering & Computing, vol. 38, no. 4, pp. 465–468, 2000
14. Generalization, discrimination, and multiple categorization using adaptive resonance theory
    IEEE Transactions on Neural Networks, vol. 10, no. 4, pp. 757–767, 1999
15. Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI
    IEEE Journal of Solid-State Circuits, vol. 34, no. 1, pp. 80–84, 1999
16. Reconfigurable pipelined 2-D convolvers for fast digital signal processing
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 3, pp. 299–308, 1999
17. A comparison of self-organizing neural networks for fast clustering of radar pulses
    Signal Processing, vol. 64, no. 3, pp. 249–269, 1998
18. Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, no. 2, pp. 161–174, 1997
19. Timing analysis speed-up using a hierarchical and a multimode approach
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 2, pp. 244–255, 1996
20. Bounds on the performance of partial selection networks
    IEEE Transactions on Communications, vol. 43, no. 2, pp. 1800–1809, 1995
21. An application-specific processor dedicated to Kalman-filter-based correction of spectrometric data
    IEEE Transactions on Instrumentation and Measurement, vol. 44, no. 3, pp. 720–724, 1995
22. A new efficient algorithmic-based SEU tolerant system architecture
    IEEE Transactions on Nuclear Science, vol. 42, no. 6, pp. 1599–1606, 1995
23. Equivalence proofs of some yield modeling methods for defect-tolerant integrated circuits
    IEEE Transactions on Computers, vol. 44, no. 5, pp. 724–728, 1995
24. An architectural approach for increasing clock frequency and communication speed in monolithic WSI systems
    IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, vol. 17, no. 3, pp. 362–368, 1994
25. Pipelining communications in large VLSI/ULSI systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, no. 1, pp. 1–10, 1994
26. A fast method to evaluate the optimum number of spares in defect-tolerant integrated circuits
    IEEE Transactions on Computers, vol. 43, no. 6, pp. 687–697, 1994
27. An integrated structure for Kalman-filter-based measurand reconstruction
    IEEE Transactions on Instrumentation and Measurement, vol. 43, no. 3, pp. 403–410, 1994
28. A systolic architecture for fast stack sequential decoders
    IEEE Transactions on Communications, vol. 42, no. 2/3/4, pp. 324–335, 1994
29. A multiprocessor architecture for multiple path stack sequential decoders
    IEEE Transactions on Communications, vol. 42, no. 2/3/4, pp. 951–957, 1994
30. New advances in microelectronics education: a Canadian model
    IEEE Transactions on Education, vol. 36, no. 1, pp. 141–147, 1993
31. VLSI design of an M-path decoder IC suitable for bidirectional decoding of convolutional codes
    Microelectronics Journal, vol. 24, no. 5, pp. 565–576, 1993
32. Test quality of hierarchical defect-tolerant integrated circuits
    Journal of Electronic Testing, vol. 3, no. 1, pp. 93–102, 1992
33. New VLSI architectures for fast soft-decision threshold decoders
    IEEE Transactions on Communications, vol. 39, no. 2, pp. 200–207, 1991
34. Optimization of resistively hardened latches
    IEEE Transactions on Nuclear Science, vol. 37, no. 1, pp. 7–14, 1990