Janusz Starzyk

Janusz Starzyk received the M.S. degree in applied mathematics and Ph.D. degree in electrical engineering from Warsaw University of Technology, Warsaw, Poland. From 1977 to 1981, he was an Assistant Professor at the Institute of Electronics Fundamentals, Warsaw University of Technology, Warsaw, Poland. From 1981 to 1983, he was a Postdoctorate Fellow and a Research Engineer at McMaster University, Hamilton, Canada. In 1983, he joined the Department of Electrical and Computer Engineering, Ohio University, Athens, Ohio, where he is currently a Professor of EECS. He has cooperated with the National Institute of Standards and Technology. He has been a consultant to ATT Bell Laboratories, Sarnoff Research, Sverdrup Technology, Magnolia Broadband, and Magnetek Corp. In 1991, he was a Visiting Professor at University of Florence, Italy. He was a Visiting Researcher at Redstone Arsenal US Army Test, Measurement, and Diagnostic Activity and at Wright Labs Advanced Systems Research and ATR Technology Development. He is an author or a coauthor of over 170 refereed journal and conference papers. Since 1993, he is the president of Artificial Neural Systems incorporated in Ohio. His current research is in the areas of embodied intelligence, sparse hierarchically organized spatiotemporal memories, self-organizing learning machines, and neural networks.

Biography Updated on 11 September 2007

Articles in Scholarly Journals [Incomplete List]

  1. GPS signal acquisition using the repeatability of successive code phase measurements
    GPS Solutions, 2007
  2. Self-organizing learning array and its application to economic and financial problems
    Information Sciences, vol. 177, no. 5, pp. 1180–1192, 2007
  3. A Novel Low-Power Logic Circuit Design Scheme
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 2, pp. 176–180, 2007
  4. Low-Power Tunable Analog Circuit Blocks Based on Nanoscale Double-Gate MOSFETs
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 7, pp. 571–575, 2007
  5. Anticipation-Based Temporal Sequences Learning in Hierarchical Structure
    IEEE Transactions on Neural Networks, vol. 18, no. 2, pp. 344–358, 2007
  6. A Self-Organizing Learning Array System for Power Quality Classification Based on Wavelet Transform
    IEEE Transactions on Power Delivery, vol. 21, no. 1, pp. 286–295, 2006
  7. Associative Learning in Hierarchical Self-Organizing Learning Arrays
    IEEE Transactions on Neural Networks, vol. 17, no. 6, pp. 1460–1470, 2006
  8. Self-Organizing Learning Array
    IEEE Transactions on Neural Networks, vol. 16, no. 2, pp. 355–363, 2005
  9. A Cost-Effective Approach to the Design and Layout of a 14-b Current-Steering DAC Macrocell
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 51, no. 1, pp. 196–200, 2004
  10. Entropy-Based Optimum Test Points Selection for Analog Fault Dictionary Techniques
    IEEE Transactions on Instrumentation and Measurement, vol. 53, no. 3, pp. 754–761, 2004
  11. Dynamic Probability Estimator for Machine Learning
    IEEE Transactions on Neural Networks, vol. 15, no. 2, pp. 298–308, 2004
  12. Iterated wavelet transformation and signal discrimination for hrr radar target recognition
    IEEE Transactions on Systems, Man, and Cybernetics - Part A: Systems and Humans, vol. 33, no. 1, pp. 52–57, 2003
  13. Multidimensional Systems and Signal Processing, vol. 14, no. 1/3, pp. 9–24, 2003
  14. Fast direct GPS P-Code acquisition
    GPS Solutions, vol. 7, no. 3, pp. 168–175, 2003
  15. A generalized fault diagnosis method in dynamic analogue circuits
    International Journal of Circuit Theory and Applications, vol. 30, no. 5, pp. 487–510, 2002
  16. Nonrandom quantization errors in timebases
    IEEE Transactions on Instrumentation and Measurement, vol. 50, no. 4, pp. 888–892, 2001
  17. Analog Integrated Circuits and Signal Processing, vol. 28, no. 2, pp. 161–172, 2001
  18. A DC-DC charge pump design based on voltage doublers
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 48, no. 3, pp. 350–359, 2001
  19. A Mathematical Foundation for Improved Reduct Generation in Information Systems
    Knowledge and Information Systems, vol. 2, no. 2, pp. 131–146, 2000
  20. Finding ambiguity groups in low testability analog circuits
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 47, no. 8, pp. 1125–1137, 2000
  21. Determination of an optimum set of testable components in the fault diagnosis of analog linear circuits
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 46, no. 7, pp. 779–787, 1999
  22. Hierarchical analysis of high frequency interconnect networks
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 5, pp. 658–664, 1994
  23. CMOS current mode winner-take-all circuit with both excitatory and inhibitory feedback
    Electronics Letters, vol. 29, no. 10, p. 908, 1993
  24. A decomposition approach for testing large analog networks
    Journal of Electronic Testing, vol. 3, no. 3, pp. 181–195, 1992
  25. Flowgraph analysis of large electronic networks
    IEEE Transactions on Circuits and Systems, vol. 33, no. 3, pp. 302–315, 1986
  26. Upward topological analysis of large circuits using directed graph representation
    IEEE Transactions on Circuits and Systems, vol. 31, no. 4, pp. 410–414, 1984
  27. A unified decomposition approach for fault location in large analog circuits
    IEEE Transactions on Circuits and Systems, vol. 31, no. 7, pp. 609–622, 1984
  28. Evaluation of faulty elements within linear subnetworks
    International Journal of Circuit Theory and Applications, vol. 12, no. 1, pp. 23–37, 1984
  29. Multiport approach to multiple-fault location in analog circuits
    IEEE Transactions on Circuits and Systems, vol. 30, no. 10, pp. 762–765, 1983
  30. Hierarchic decomposition method for the topological analysis of electronic networks
    International Journal of Circuit Theory and Applications, vol. 8, no. 4, pp. 407–417, 1980