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Articles in Scholarly Journals [Incomplete List]

1. Modeling leakage power reduction in VLSI as optimization problems
   Optimization and Engineering, vol. 8, no. 2, pp. 129–162, 2007
2. Dual-Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 1, pp. 53–66, 2007
3. Impact of technology scaling and process variations on RF CMOS devices
   Microelectronics Journal, vol. 37, no. 4, pp. 275–282, 2006
4. Low-power multi-threshold MCML: Analysis, design, and variability
   Microelectronics Journal, vol. 37, no. 10, pp. 1097–1104, 2006
5. Design and optimization of MOS current mode logic for parameter variations
   Integration, the VLSI Journal, vol. 38, no. 3, pp. 417–437, 2005
6. POMR: A Power-Aware Interconnect Optimization Methodology
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 3, pp. 297–307, 2005
7. MOS Current Mode Circuits: Analysis, Design, and Variability
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 885–898, 2005
8. Design and optimization of multithreshold cmos (mtcmos) circuits
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1324–1342, 2003
9. Impact of technology scaling on CMOS logic styles
   IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 8, pp. 577–588, 2002
10. Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 2, pp. 71–78, 2002