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Articles in Scholarly Journals [Incomplete List]

1. Arbiter synthesis approach for SoC multi-processor systems
   Computers & Electrical Engineering, vol. 34, no. 1, pp. 63–77, 2008
2. System on Chips optimization using ABV and automatic generation of SystemC codes
   Microprocessors and Microsystems, vol. 31, no. 7, pp. 433–444, 2007
3. An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC
   Computers & Electrical Engineering, vol. 31, no. 4-5, pp. 282–302, 2005
4. A novel formal verification approach for RTL hardware IP cores
   Computer Standards & Interfaces, vol. 27, no. 6, pp. 637–651, 2005
5. High performance architecture of integrated protocols for encoded video application
   Computer Standards & Interfaces, vol. 26, no. 4, pp. 301–315, 2004
6. Co-simulation and communication synthesis approach for intellectual properties based SoCs
   Computers & Electrical Engineering, vol. 30, no. 5, pp. 361–381, 2004
7. Protocol architecture for MPEG-2 video over a high speed network
   IEE Proceedings - Communications, vol. 151, no. 1, p. 8, 2004
8. Communication synthesis techniques for multiprocessor systems
   International Journal of Electronics, vol. 89, no. 1, pp. 55–76, 2002
9. Problems in pattern classification in high dimensional spaces: behavior of a class of combined neuro-fuzzy classifiers
   Fuzzy Sets and Systems, vol. 128, no. 1, pp. 15–33, 2002
10. Design of telecommunication electronic systems using a hardware/software co-design methodology
    International Journal of Electronics, vol. 88, no. 3, pp. 255–270, 2001
11. TCP flow control technique for an interworking interface: hardware implementation
    Computer Standards & Interfaces, vol. 23, no. 5, pp. 383–397, 2001
12. Rapid prototyping of an ATM programmable associative operator
    Journal of Systems Architecture, vol. 46, no. 13, pp. 1159–1173, 2000
13. VLSI design of 1-D DWT architecture with parallel filters
    Integration, the VLSI Journal, vol. 29, no. 2, pp. 181–207, 2000
14. Design of New Optimized Architecture Processor for DWT
    Real-Time Imaging, vol. 6, no. 4, pp. 297–312, 2000