Charles E. Stroud

Charles E. Stroud was graduated from the University of Kentucky with BSEE degree in 1976 and MSEE degree in 1977. He spent 15 years at Bell Labs where he was a Distinguished Member of Technical Staff designing VLSI devices and printed circuit boards for computer telecommunications and systems. Of the 21 production VLSI devices he designed 16 incorporated Built-In Self-Test (BIST) including the first BIST for Random Access Memories, the first completely self-testing chip using Circular BIST, and the first BIST for mixed-signal systems. He received a Ph.D. degree in electrical engineering and computer science from the University of Illinois at Chicago in 1991. He left Bell Labs in 1993 and has been in academia since that time where his accomplishments include the first BIST for Field Programmable Gate Arrays. He holds 16 US patents for various BIST approaches for VLSI devices and FPGAs. He has published over 130 journal and conference papers with two best paper awards. He is author of the book entitled A Designer’s Guide to Built-In Self-Test and coeditor of a new book entitled System-on-Chip Test Architectures. He has served on the editorial boards for IEEE Transactions on VLSI Systems, IEEE Design & Test of Computers, and Journal of Electronic Testing: Theory & Applications. In addition, he has served on program committees for IEEE International Test Conference, IEEE International On-Line Test Symposium, IEEE North Atlantic Test Workshop, ACM International Symposium on Field Programmable Gate Arrays, IEEE International Application Specific Integrated Circuits Conference, and ACM/IEEE International Workshop on Hardware/Software Co-Design. He is a Member of Tau Beta Pi, Eta Kappa Nu, and a Fellow of IEEE and IEEE Computer Society.

Biography Updated on 11 January 2008

Personal Home Page

http://www.eng.auburn.edu/users/strouce

Articles in Scholarly Journals [Incomplete List]

  1. FPGA-Based Analog Functional Measurements for Adaptive Control in Mixed-Signal Systems
    IEEE Transactions on Industrial Electronics, vol. 54, no. 4, pp. 1885–1897, 2007
  2. Online Fault Tolerance for FPGA Logic Blocks
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 2, pp. 216–226, 2007
  3. Automatic Linearity and Frequency Response Tests With Built-in Pattern Generator and Analyzer
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 6, pp. 561–572, 2006
  4. An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
    Journal of Electronic Testing, vol. 22, no. 3, pp. 239–253, 2006
  5. Online BIST and BIST-Based Diagnosis of FPGA Logic Blocks
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 12, pp. 1284–1294, 2004
  6. Journal of Electronic Testing, vol. 19, no. 5, pp. 549–558, 2003
  7. BIST-based test and diagnosis of FPGA logic blocks
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 159–172, 2001
  8. Journal of Electronic Testing, vol. 16, no. 6, pp. 635–640, 2000
  9. Modeling, design, and performance analysis of a parallel hybrid data/command driven architecture system and its scalable dynamic load balancing circuit
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 1, pp. 22–40, 1997
  10. Multiple error detection and identification via signature analysis
    Journal of Electronic Testing, vol. 7, no. 3, pp. 193–207, 1995
  11. Reliability of majority voting based VLSI fault-tolerant circuits
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, no. 4, pp. 516–521, 1994
  12. Testability and test generation for majority voting fault-tolerant circuits
    Journal of Electronic Testing, vol. 4, no. 3, pp. 201–214, 1993
  13. Metastability of CMOS master/slave flip-flops
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 10, pp. 734–740, 1992
  14. Behavioral model synthesis with Cones
    IEEE Design & Test of Computers, vol. 5, no. 3, pp. 22–30, 1988
  15. Automated BIST for sequential logic synthesis
    IEEE Design & Test of Computers, vol. 5, no. 6, pp. 22–32, 1988
  16. Identification of nosean in sodalite and conversion of nosean to sodalite
    Materials Research Bulletin, vol. 15, no. 5, pp. 595–605, 1980
  17. Journal of Physical Chemistry, vol. 83, no. 18, pp. 2378–2382, 1979