Andre Ivanov

Personal Home Page

http://www.ece.ubc.ca/~ivanov

Articles in Scholarly Journals [Incomplete List]

  1. Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip
    Integration, the VLSI Journal, vol. 40, no. 2, pp. 149–160, 2007
  2. Test scheduling for built-in self-tested embedded SRAMs with data retention faults
    IET Computers & Digital Techniques, vol. 1, no. 3, p. 256, 2007
  3. Two-Point Maximum Entropy Noise Discrimination in Spectra Over a Range of Baseline Offsets and Signal-to-Noise Ratios
    Applied Spectroscopy, vol. 61, no. 2, pp. 157–164, 2007
  4. Fast Detection of Data Retention Faults and Other SRAM Cell Open Defects
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 167–180, 2006
  5. System-on-Chip: Reuse and Integration
    Proceedings of the IEEE, vol. 94, no. 6, pp. 1050–1069, 2006
  6. Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
    IEEE Transactions on Computers, vol. 54, no. 8, pp. 1025–1040, 2005
  7. Design, Synthesis, and Test of Networks on Chips
    IEEE Design and Test of Computers, vol. 22, no. 5, pp. 404–413, 2005
  8. Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research
    IEEE Design and Test of Computers, vol. 22, no. 5, pp. 399–403, 2005
  9. Crosstalk Bounded Uncorrelated Jitter (BUJ) for High-Speed Interconnects
    IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 5, pp. 1800–1810, 2005
  10. Timing analysis of network on chip architectures for MP-SoC platforms
    Microelectronics Journal, vol. 36, no. 9, pp. 833–845, 2005
  11. A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices
    Journal of Electronic Testing, vol. 21, no. 6, pp. 621–630, 2005
  12. An Analog Circuit Fault Characterization Methodology
    Journal of Electronic Testing, vol. 21, no. 2, pp. 127–134, 2005
  13. A 0.18 μm CMOS pipelined encoder for a 5 GS/s 4-bit flash analogue-to-digital converter
    Canadian Journal of Electrical and Computer Engineering, vol. 30, no. 4, pp. 183–187, 2005
  14. Calibration-free heat source localisation in ICs entirely covered by metal layers
    Electronics Letters, vol. 40, no. 4, p. 241, 2004
  15. Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates
    IEEE Design and Test of Computers, vol. 21, no. 4, pp. 274–276, 2004
  16. Jitter models for the design and test of Gbps-speed serial interconnects
    IEEE Design and Test of Computers, vol. 21, no. 4, pp. 302–313, 2004
  17. Indirect Test Architecture for SoC Testing
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 7, pp. 1128–1142, 2004
  18. An all-digital DFT scheme for testing catastrophic faults in PLLs
    IEEE Design & Test of Computers, vol. 20, no. 1, pp. 60–67, 2003
  19. Journal of Electronic Testing, vol. 19, no. 3, pp. 353–357, 2003
  20. Localisation of devices acting as heat sources in ICs covered entirely by metal layers
    Electronics Letters, vol. 39, no. 20, p. 1440, 2003
  21. Journal of Electronic Testing, vol. 18, no. 3, pp. 295–304, 2002
  22. Embedded servo loop for ADC linearity testing
    Microelectronics Journal, vol. 33, no. 10, pp. 773–780, 2002
  23. On the detectability of CMOS floating gate transistor faults
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, pp. 116–128, 2001
  24. Journal of Electronic Testing, vol. 16, no. 6, pp. 631–634, 2000
  25. Programmable BIST space compactors
    IEEE Transactions on Computers, vol. 45, no. 12, pp. 1393–1404, 1996
  26. Fast signature computation for BIST linear compactors
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 8, pp. 1037–1044, 1995
  27. Reducing hardware with fuzzy multiple signature analysis
    IEEE Design & Test of Computers, vol. 12, no. 1, pp. 68–74, 1995
  28. A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes
    Journal of Electronic Testing, vol. 6, no. 1, pp. 75–84, 1995
  29. Single-reference multiple intermediate signature (SREMIS) analysis for BIST
    IEEE Transactions on Computers, vol. 44, no. 6, pp. 817–825, 1995
  30. On minimizing aliasing in scan-based compaction
    Journal of Electronic Testing, vol. 5, no. 1, pp. 83–90, 1994
  31. Sequential faults and aliasing
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 7, pp. 1068–1074, 1993
  32. Notes on multiple input signature analysis
    IEEE Transactions on Computers, vol. 42, no. 2, pp. 228–234, 1993
  33. A multiple signature compaction scheme for BIST
    Microelectronics Journal, vol. 23, no. 3, pp. 205–214, 1992
  34. Performance of signature analysis: a survey of bounds, exact, and heuristic algorithms
    Integration, the VLSI Journal, vol. 13, no. 1, pp. 17–38, 1992
  35. Computing the probability of undetected error for shortened cyclic codes
    IEEE Transactions on Communications, vol. 40, no. 3, pp. 494–499, 1992
  36. Using an asymmetric error model to study aliasing in signature analysis registers
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 1, pp. 16–25, 1992
  37. Count-based BIST compaction schemes and aliasing probability computation
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 6, pp. 768–777, 1992
  38. Iterative algorithms for computing aliasing probabilities
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 2, pp. 260–265, 1991
  39. An analysis of the probabilistic behavior of linear feedback signature registers
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 10, pp. 1074–1088, 1989
  40. Dynamic testability measures for ATPG
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 5, pp. 598–608, 1988