Nagarajan Ranganathan

Personal Home Page

http://www.cse.usf.edu/index.php?id=25&par=172

Articles in Scholarly Journals [Incomplete List]

  1. Multievent Crisis Management Using Noncooperative Multistep Games
    IEEE Transactions on Computers, vol. 56, no. 5, pp. 577–589, 2007
  2. A Reflection on the TVLSI Editorial Process and the Announcement of a New Editor-In-Chief
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 1, pp. 1–4, 2007
  3. A Dual Voltage-Frequency VLSI Chip for Image Watermarking in DCT Domain
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 5, pp. 394–398, 2006
  4. A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing
    ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 3, pp. 711–739, 2006
  5. Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory
    IEEE Transactions on Computers, vol. 55, no. 8, pp. 1011–1023, 2006
  6. Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
    ACM Transactions on Design Automation of Electronic Systems, vol. 10, no. 2, pp. 330–353, 2005
  7. Simultaneous Peak and Average Power Minimization During Datapath Scheduling
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 52, no. 6, pp. 1157–1165, 2005
  8. A VLSI Architecture for Watermarking in a Secure Still Digital Camera$(hboxS^2hboxDC)$Design
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 7, pp. 808–818, 2005
  9. A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera<tex>$(hboxS^2hboxDC)$</tex>Design (Corrected)*
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 1002–1012, 2005
  10. LECTOR: A Technique for Leakage Reduction in CMOS Circuits
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 196–205, 2004
  11. Editorial
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 1, pp. 1–11, 2004
  12. A Framework for Energy and Transient Power Reduction During Behavioral Synthesis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 6, pp. 562–572, 2004
  13. Another Step in the Right Direction for TVLSI
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 7, pp. 673–673, 2004
  14. Cascaded Bayesian inferencing for switching activity estimation with correlated inputs
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 12, pp. 1360–1370, 2004
  15. Stochastic channel-adaptive rate control for wireless video transmission
    Pattern Recognition Letters, vol. 25, no. 7, pp. 793–806, 2004
  16. Multiterminal net routing for partial crossbar-based multi-FPGA systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, pp. 71–78, 2003
  17. Routing on field-programmable switch matrices
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 2, pp. 283–287, 2003
  18. Switching activity estimation of VLSI circuits using bayesian networks
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 4, pp. 558–567, 2003
  19. Petri net modeling of gate and interconnect delays for power estimation
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 5, pp. 921–927, 2003
  20. A game theoretic approach for power optimization during behavioral synthesis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1031–1043, 2003
  21. IDUTC: an intelligent decision-making system for urban traffic-control applications
    IEEE Transactions on Vehicular Technology, vol. 50, no. 3, pp. 816–829, 2001
  22. A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 2, pp. 407–410, 2001
  23. VBR video traffic management using a predictor-based architecture
    Computer Communications, vol. 23, no. 1, pp. 62–70, 2000
  24. Utilization of cache area in on-chip multiprocessor
    Microprocessors and Microsystems, vol. 24, no. 8, pp. 429–436, 2000
  25. Supporting object accesses in a Java processor
    IEE Proceedings - Computers and Digital Techniques, vol. 147, no. 6, p. 435, 2000
  26. Computing the bivariate Gaussian probability integral
    IEEE Signal Processing Letters, vol. 6, no. 6, pp. 129–131, 1999
  27. Adaptive VBR video traffic management for higher utilization of ATM networks
    ACM SIGCOMM Computer Communication Review, vol. 28, no. 3, pp. 27–40, 1998
  28. Sequential tests for integrated-circuit failures
    IEEE Transactions on Reliability, vol. 47, no. 4, pp. 463–471, 1998
  29. A generalized sequential sign detector for binary hypothesis testing
    IEEE Signal Processing Letters, vol. 5, no. 11, pp. 295–297, 1998
  30. EQUIVALENT CONSTANT AMPLITUDE CONCEPTS EXAMINED UNDER FATIGUE CRACK PROPAGATION BY BLOCK LOADING
    Fatigue & Fracture of Engineering Materials and Structures, vol. 19, no. 8, pp. 997–1008, 1996
  31. A lossless image compression algorithm using variable block size segmentation
    IEEE Transactions on Image Processing, vol. 4, no. 10, pp. 1396–1406, 1995
  32. A high speed systolic architecture for labeling connected components in an image
    IEEE Transactions on Systems, Man, and Cybernetics, vol. 25, no. 3, pp. 415–423, 1995
  33. CASM: a VLSI chip for approximate string matching
    IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 17, no. 8, pp. 824–830, 1995
  34. VLSI architectures for high-speed range estimation
    IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 17, no. 9, pp. 894–899, 1995
  35. JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard
    Proceedings of the IEEE, vol. 83, no. 2, pp. 247–258, 1995
  36. Fatigue crack propagation mechanisms in an aluminium lithium alloy
    Acta Metallurgica et Materialia, vol. 43, no. 3, pp. 1029–1035, 1995
  37. On micromechanisms of fatigue crack growth in the 8090 T651 aluminium-lithium alloy
    Materials Science and Engineering A, vol. 187, no. 1, pp. 37–42, 1994
  38. High-speed VLSI designs for Lempel-Ziv-based data compression
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 40, no. 2, pp. 96–106, 1993
  39. SIGMA: a VLSI systolic array implementation of a Galois field GF(2/sup m/) based multiplication and division algorithm
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 1, pp. 22–30, 1993
  40. MARVLE: a VLSI chip for data compression using tree-based codes
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 2, pp. 203–214, 1993
  41. VLSI architectures for polygon recognition
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 4, pp. 398–407, 1993
  42. Efficient VLSI designs for data transformation of tree-based codes
    IEEE Transactions on Circuits and Systems, vol. 38, no. 3, pp. 306–314, 1991
  43. Changes of elastic constants associated with fatigue damage in an aluminium alloy
    Materials Science and Engineering A, vol. 147, no. 2, pp. 161–166, 1991
  44. Enhancing arithmetic and tree-based coding
    Information Processing & Management, vol. 25, no. 3, pp. 293–305, 1989
  45. A VLSI architecture for computing scale space
    Computer Vision, Graphics, and Image Processing, vol. 43, no. 2, pp. 178–204, 1988
  46. Effect of R ratio and ?K level on the hysteretic energy dissipated during fatigue crack propagation
    Scripta Metallurgica, vol. 21, no. 8, pp. 1045–1049, 1987
  47. A contribution to the study of fatigue crack retardation in vacuum
    Engineering Fracture Mechanics, vol. 11, no. 4, pp. 775–789, 1979