Dimitrios Soudris
National Technical University of Athens, Greece
Personal Home Page
http://www.microlab.ece.ntua.gr/?q=en/people/academicstaff/dsoudris
Articles in Scholarly Journals [Incomplete List]
- Exploration methodology of dynamic data structures in multimedia and network applications for embedded platforms☆
Journal of Systems Architecture, 2008 - Systematic methodology for exploration of performance – Energy trade-offs in network applications using Dynamic Data Type refinement☆
Journal of Systems Architecture, vol. 53, no. 7, pp. 417–436, 2007 - Preface
Integration, the VLSI Journal, vol. 40, no. 2, pp. 61–61, 2007 - Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications?
Integration, the VLSI Journal, vol. 40, no. 2, pp. 74–93, 2007 - Systematic methodology for designing low power direct digital frequency synthesisers
IET Circuits, Devices & Systems, vol. 1, no. 4, p. 293, 2007 - Automated framework for partitioning DSP applications in hybrid reconfigurable platforms
Microprocessors and Microsystems, vol. 31, no. 1, pp. 1–14, 2007 - Preface of Special Issue on VLSI Design and Test
Microelectronic Engineering, vol. 84, no. 2, pp. 193–193, 2007 - Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance?
Computer Communications, vol. 29, no. 13-14, pp. 2612–2620, 2006 - Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors
The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 44, no. 1-2, pp. 153–171, 2006 - Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems?
Integration, the VLSI Journal, vol. 39, no. 2, pp. 113–130, 2006 - A Combined DMA and Application-Specific Prefetching Approach for Tackling the Memory Latency Bottleneck
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 3, pp. 279–291, 2006 - Systematic dynamic memory management design methodology for reduced memory footprint
ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 2, pp. 465–489, 2006 - Fine-grain reconfigurable platform: FPGA hardware design and software toolset development
Journal of Physics: Conference Series, vol. 10, pp. 352–356, 2005 - Journal of Circuits, Systems, and Computers, vol. 14, no. 2, p. 281, 2005
- A method for partitioning applications in hybrid reconfigurable architectures
Design Automation for Embedded Systems, vol. 10, no. 1, pp. 27–47, 2005 - A complete platform and toolset for system implementation on fine-grain reconfigurable hardware
Microprocessors and Microsystems, vol. 29, no. 6, pp. 247–259, 2005 - Behavioral-level event-driven power management for DECT digital receivers
Microelectronics Journal, vol. 36, no. 2, pp. 163–172, 2005 - Editorial: Power and timing modelling, optimisation and simulation
IEE Proceedings - Computers and Digital Techniques, vol. 152, no. 6, p. 721, 2005 - A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications
IEICE Transactions on Information and Systems, vol. E88-D, no. 7, pp. 1369–1380, 2005 - Colour quantisation technique based on image decomposition and its embedded system implementation
IEE Proceedings - Vision, Image, and Signal Processing, vol. 151, no. 6, p. 511, 2004 - The low power analogue and digital baseband processing parts of a novel multimode DECT/GSM/DCS1800 terminal
Microelectronics Journal, vol. 35, no. 7, pp. 609–620, 2004 - Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms
Real-Time Imaging, vol. 9, no. 6, pp. 371–386, 2003 - A fast and accurate delay dependent method for switching estimation of large combinational circuits
Journal of Systems Architecture, vol. 48, no. 4-5, pp. 113–124, 2002 - Power and performance exploration of embedded systems executing multimedia kernels
IEE Proceedings - Computers and Digital Techniques, vol. 149, no. 4, p. 164, 2002 - VLSI methodology for the design of RNS and QRNS full adder based converters
IEE Proceedings - Circuits, Devices and Systems, vol. 149, no. 4, p. 241, 2002 - A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model
VLSI Design, vol. 12, no. 1, pp. 69–79, 2001 - A Fast and Accurate Method of Power Estimation for Logic Level Networks
VLSI Design, vol. 12, no. 2, pp. 205–219, 2001 - Low-power design of direct conversion baseband DECT receiver
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 12, pp. 1121–1131, 2001 - A New Method for Low Power Design of Two-Level Logic Circuits
VLSI Design, vol. 9, no. 2, pp. 147–157, 1999 - Modelling and Simulation in Materials Science and Engineering, vol. 7, no. 4, pp. 631–640, 1999
- Design methodology for systematic derivation of fault-tolerant processor array architectures
International Journal of Electronics, vol. 84, no. 6, pp. 615–624, 1998 - Quaternary voltage-mode CMOS circuits for multiple-valued logic
IEE Proceedings - Circuits, Devices and Systems, vol. 145, no. 2, p. 71, 1998 - Modelling and Simulation in Materials Science and Engineering, vol. 5, no. 5, pp. 439–450, 1997
- A VLSI design methodology for RNS full adder-based inner product architectures
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 44, no. 4, pp. 315–318, 1997 - Design methodology for the implementation of multidimensional circular convolution
IEE Proceedings - Circuits, Devices and Systems, vol. 144, no. 6, p. 323, 1997 - Journal of Circuits, Systems, and Computers, vol. 6, no. 3, p. 243, 1996
- A systematic methodology for mapping DSP algorithms onto multilevel array architectures
International Journal of Electronics, vol. 79, no. 5, pp. 507–518, 1995 - Mapping iterative algorithims on regular processor arrays without using uniform recurrent equations
Microprocessing and Microprogramming, vol. 31, no. 1-5, pp. 53–58, 1991