Articles in Scholarly Journals [Incomplete List]

1. ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator
   VLSI Design, vol. 2008, Article ID 482159, 8 pages, 2008
2. An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs
   Journal of Electronic Testing, vol. 22, no. 2, pp. 161–172, 2006
3. A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs
   IEEE Design and Test of Computers, vol. 23, no. 3, pp. 234–243, 2006
4. Simulating Resistive-Bridging and Stuck-At Faults
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 2181–2192, 2006
5. Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs
   Journal of Electronic Testing, vol. 21, no. 1, pp. 43–55, 2005
6. Modeling Feedback Bridging Faults with Non-Zero Resistance
   Journal of Electronic Testing, vol. 21, no. 1, pp. 57–69, 2005
7. Applying the Oscillation Test Strategy to FPAA?s Configurable Analog Blocks
   Journal of Electronic Testing, vol. 21, no. 2, pp. 135–146, 2005
8. Delay Testing Viability of Gate Oxide Short Defects
   Journal of Computer Science and Technology, vol. 20, no. 2, pp. 195–200, 2005
9. Built-in self-test of global interconnects of field programmable analog arrays
   Microelectronics Journal, vol. 36, no. 12, pp. 1112–1123, 2005
10. A compact DC model of gate oxide short defect
    Microelectronic Engineering, vol. 72, no. 1-4, pp. 140–148, 2004
11. Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors
    Journal of Electronic Testing, vol. 20, no. 3, pp. 257–267, 2004
12. Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure
    Journal of Electronic Testing, vol. 20, no. 4, pp. 375–387, 2004
13. A New FPGA for DSP Applications Integrating BIST Capabilities
    Journal of Electronic Testing, vol. 20, no. 4, pp. 423–431, 2004
14. Journal of Circuits, Systems, and Computers, vol. 12, no. 2, p. 143, 2003
15. An all-digital DFT scheme for testing catastrophic faults in PLLs
    IEEE Design & Test of Computers, vol. 20, no. 1, pp. 60–67, 2003
16. Extending ieee IEEE std. 1149.4 analog boundary modules to enhance mixed-signal test
    IEEE Design & Test of Computers, vol. 20, no. 2, pp. 32–39, 2003
17. A-to-D converters static error detection from dynamic parameter measurement
    Microelectronics Journal, vol. 34, no. 10, pp. 945–953, 2003
18. Journal of Electronic Testing, vol. 19, no. 4, pp. 469–479, 2003
19. Journal of Electronic Testing, vol. 19, no. 4, pp. 377–386, 2003
20. Analog built-in saw-tooth generator for ADC histogram test
    Microelectronics Journal, vol. 33, no. 10, pp. 781–789, 2002
21. Improving defect detection in static-voltage testing
    IEEE Design & Test of Computers, vol. 19, no. 6, pp. 83–89, 2002
22. Journal of Electronic Testing, vol. 17, no. 2, pp. 139–147, 2001
23. Journal of Electronic Testing, vol. 17, no. 3/4, pp. 255–266, 2001
24. Journal of Electronic Testing, vol. 17, no. 3/4, pp. 283–290, 2001
25. On the detectability of CMOS floating gate transistor faults
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, pp. 116–128, 2001
26. Journal of Electronic Testing, vol. 16, no. 3, pp. 259–267, 2000
27. Journal of Electronic Testing, vol. 16, no. 3, pp. 289–299, 2000
28. Journal of Electronic Testing, vol. 16, no. 5, pp. 513–520, 2000
29. Journal of Electronic Testing, vol. 14, no. 1/2, pp. 159–167, 1999
30. Journal of Electronic Testing, vol. 14, no. 1/2, pp. 13–22, 1999
31. Testing the interconnect of RAM-based FPGAs
    IEEE Design & Test of Computers, vol. 15, no. 1, pp. 45–50, 1998
32. On-chip signature analyser for analogue circuit testing
    Electronics Letters, vol. 32, no. 24, p. 2185, 1996
33. Current testing in dynamic CMOS circuits
    Journal of Electronic Testing, vol. 6, no. 1, pp. 127–131, 1995
34. Realistic fault model for external shorts in MOS technologies
    Electronics Letters, vol. 29, no. 9, p. 813, 1993
35. Electrical analysis and modeling of floating-gate fault
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 11, pp. 1450–1458, 1992
36. Topology dependence of floating gate faults in MOS integrated circuits
    Electronics Letters, vol. 22, no. 3, p. 152, 1986
37. FSPICE: a tool for fault modelling in MOS circuits
    Integration, the VLSI Journal, vol. 3, no. 3, pp. 245–255, 1985