Jacob A. Abraham

Articles in Scholarly Journals [Incomplete List]

  1. Predicting mixed-signal dynamic performance using optimised signature-based alternate test
    IET Computers & Digital Techniques, vol. 1, no. 3, p. 159, 2007
  2. Improved verification of hardware designs through antecedent conditioned slicing
    International Journal on Software Tools for Technology Transfer, vol. 9, no. 1, pp. 89–101, 2006
  3. A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor
    Formal Methods in System Design, vol. 27, no. 1-2, pp. 67–112, 2005
  4. Efficient Model Checking of Hardware Using Conditioned Slicing
    Electronic Notes in Theoretical Computer Science, vol. 128, no. 6, pp. 279–294, 2005
  5. Subband Filtering for Time and Frequency Analysis of Mixed-Signal Circuit Testing
    IEEE Transactions on Instrumentation and Measurement, vol. 53, no. 2, pp. 602–611, 2004
  6. Test data compression and test time reduction using an embedded microprocessor
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 5, pp. 853–862, 2003
  7. A comprehensive signature analysis scheme for oscillation-test
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1409–1423, 2003
  8. Journal of Electronic Testing, vol. 19, no. 2, pp. 149–160, 2003
  9. Formal Methods in System Design, vol. 21, no. 1, pp. 95–101, 2002
  10. Journal of Electronic Testing, vol. 17, no. 5, pp. 395–408, 2001
  11. Design and development paradigm for industrial formal verification CAD tools
    IEEE Design & Test of Computers, vol. 18, no. 4, pp. 26–35, 2001
  12. Validating PowerPC microprocessor custom memories
    IEEE Design & Test of Computers, vol. 17, no. 4, pp. 61–76, 2000
  13. Journal of Electronic Testing, vol. 16, no. 1/2, pp. 67–81, 2000
  14. Journal of Electronic Testing, vol. 15, no. 1/2, pp. 173–189, 1999
  15. Design and evaluation of system-level checks for on-line control flow error detection
    IEEE Transactions on Parallel and Distributed Systems, vol. 10, no. 6, pp. 627–641, 1999
  16. An efficient filter-based approach for combinational verification
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 11, pp. 1542–1557, 1999
  17. Signature analysis for analog and mixed-signal circuit test response compaction
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 6, pp. 540–546, 1998
  18. Journal of Electronic Testing, vol. 13, no. 2, pp. 137–148, 1998
  19. Memory distribution: Techniques and practice for CAD applications
    Parallel Computing, vol. 24, no. 11, pp. 1597–1615, 1998
  20. Abstraction techniques for validation coverage analysis and test generation
    IEEE Transactions on Computers, vol. 47, no. 1, pp. 2–14, 1998
  21. Journal of Electronic Testing, vol. 11, no. 2, pp. 119–129, 1997
  22. Automatic verification of implementations of large circuits against HDL specifications
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 3, pp. 217–228, 1997
  23. Indexed BDDs: algorithmic advances in techniques to represent and verify Boolean functions
    IEEE Transactions on Computers, vol. 46, no. 11, pp. 1230–1245, 1997
  24. Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 10, pp. 1278–1285, 1996
  25. Analog testing with time response parameters
    IEEE Design & Test of Computers, vol. 13, no. 2, pp. 18–25, 1996
  26. A unified approach for fault simulation of linear mixed-signal circuits
    Journal of Electronic Testing, vol. 9, no. 1-2, pp. 29–41, 1996
  27. Hierarchical fault modeling for linear analog circuits
    Analog Integrated Circuits and Signal Processing, vol. 10, no. 1-2, pp. 89–99, 1996
  28. Efficient techniques for the analysis of algorithm-based fault tolerance (ABFT) schemes
    IEEE Transactions on Computers, vol. 45, no. 4, pp. 499–503, 1996
  29. FERRARI: a flexible software-based fault and error injection system
    IEEE Transactions on Computers, vol. 44, no. 2, pp. 248–260, 1995
  30. BiCMOS logic testing
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, no. 2, pp. 241–248, 1994
  31. An efficient critical path tracing algorithm for sequential circuits
    Microprocessing and Microprogramming, vol. 40, no. 10-12, pp. 913–916, 1994
  32. Fault simulation of linear analog circuits
    Journal of Electronic Testing, vol. 4, no. 4, pp. 345–360, 1993
  33. Fault simulation of linear analog circuits
    Analog Integrated Circuits and Signal Processing, vol. 4, no. 3, pp. 245–260, 1993
  34. A high-level approach to test generation
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 40, no. 7, pp. 483–492, 1993
  35. Benchmarking parallel processing platforms: an applications perspective
    IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 8, pp. 947–954, 1993
  36. VLSI logic and fault simulation on general-purpose parallel computers
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 3, pp. 446–460, 1993
  37. Test compaction for sequential circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 2, pp. 260–267, 1992
  38. Probabilistic verification of Boolean functions
    Formal Methods in System Design, vol. 1, no. 1, pp. 61–115, 1992
  39. Generation and evaluation of current and logic tests for switch-level sequential circuits
    Journal of Electronic Testing, vol. 3, no. 4, pp. 359–366, 1992
  40. Probabilistic evaluation of online checks in fault-tolerant multiprocessor systems
    IEEE Transactions on Computers, vol. 41, no. 5, pp. 532–541, 1992
  41. Test generation for iterative logic arrays based on an N-cube of cell states model
    IEEE Transactions on Computers, vol. 40, no. 10, pp. 1133–1148, 1991
  42. Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling
    Journal of Electronic Testing, vol. 2, no. 4, pp. 351–372, 1991
  43. The use of RTL descriptions in accurate timing verification and test generation (VLSI)
    IEEE Journal of Solid-State Circuits, vol. 26, no. 9, pp. 1230–1239, 1991
  44. Hierarchical multi-level fault simulation of large systems
    Journal of Electronic Testing, vol. 1, no. 2, pp. 139–149, 1990
  45. A reconfigurable parallel signature analyzer for concurrent error correction in DRAM
    IEEE Journal of Solid-State Circuits, vol. 25, no. 3, pp. 866–870, 1990
  46. Physical design of testable VLSI: techniques and experiments
    IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 474–481, 1990
  47. Real-number codes for fault-tolerant matrix operations on processor arrays
    IEEE Transactions on Computers, vol. 39, no. 4, pp. 426–435, 1990
  48. Algorithm-based fault tolerance on a hypercube multiprocessor
    IEEE Transactions on Computers, vol. 39, no. 9, pp. 1132–1145, 1990
  49. The testability of generalized counters under multiple faulty cells
    IEEE Transactions on Computers, vol. 39, no. 11, pp. 1378–1385, 1990
  50. Fault-tolerant FFT networks
    IEEE Transactions on Computers, vol. 37, no. 5, pp. 548–561, 1988
  51. Techniques for efficiently implementing totally self-checking checkers in MOS technology
    Computers & Mathematics with Applications, vol. 13, no. 5-6, pp. 555–566, 1987
  52. Concurrent error detection in highly structured logic arrays
    IEEE Journal of Solid-State Circuits, vol. 22, no. 4, pp. 583–594, 1987
  53. Designing for concurrent error detection in VLSI: application to a microprogram control unit
    IEEE Journal of Solid-State Circuits, vol. 22, no. 4, pp. 595–605, 1987
  54. Companson and Diagnosis of Large Replicated Files
    IEEE Transactions on Software Engineering, vol. SE-13, no. 1, pp. 15–22, 1987
  55. Adaptive interpretation as a means of exploiting complex instruction sets
    ACM SIGARCH Computer Architecture News, vol. 11, no. 3, pp. 277–282, 1983
  56. Concurrent error detection in VLSI interconnection networks
    ACM SIGARCH Computer Architecture News, vol. 11, no. 3, pp. 309–315, 1983
  57. Load Balancing in Distributed Systems
    IEEE Transactions on Software Engineering, vol. SE-8, no. 4, pp. 401–412, 1982
  58. Design of testable structures defined by simple loops
    IEEE Transactions on Circuits and Systems, vol. 28, no. 11, pp. 1079–1088, 1981
  59. A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks
    IEEE Transactions on Computers, vol. C-24, no. 5, pp. 578–584, 1975
  60. An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks
    IEEE Transactions on Computers, vol. C-23, no. 7, pp. 682–692, 1974