Wen-Ben Jone

Wen-Ben Jone received the B.S. degree in computer science in 1979, the M.S. degree in computer engineering in 1981, both from National Chiao-Tung University, Hsin-Chu, Taiwan, and the Ph.D. degree in computer engineering and science from Case Western Reserve University, Cleveland, Ohio, in 1987. In 1987, he joined the Department of Computer Science at New Mexico Institute of Mining and Technology, New Mexico, where he was promoted as an Associate Professor in 1992. From 1993 to 2000, he was with the Department of Computer Engineering and Information Science, National Chung-Cheng University, Taiwan. From 2001, he has been an Associate Professor at the Department of Electrical & Computer Engineering and Computer Science, University of Cincinnati, USA. His research interests include VLSI design for testability, built-in self-testing, memory testing, high-performance circuit testing, MEMS testing and repairing, and low-power circuit design and test. He has published more than 100 papers and holds one patent (USA). Dr. Jone served as a reviewer in these research areas in various technical journals and conferences. He is also listed in the Marquis Who's Who in the World (15th edition, 1998, 2001). He also served on the program committee of VLSI Design/CAD Symposium (1993-1997, in Taiwan), was the General Chair of 1998 VLSI Design/CAD Symposium, and served on the program committee of 1995, 1996, 2000 Asian Test Conferences, 1995-1998 Asia and South Pacific Design Automation Conference, 1998 International Conference on Chip Technology, 2000, 2007 International Symposium on Defect and Fault Tolerance in VLSI Systems, and 2002, 2003 Great Lake Symposium on VLSI. He received the Best Thesis Award from The Chinese Institute of Electrical Engineering, China, in 1981. He is a Corecipient of the 2003 IEEE Donald G.Fink Prize Paper Award. He is a Senior Member of IEEE and the IEEE Computer Society Test Technology Technical Committee.

Biography Updated on 31 January 2008

Personal Home Page

http://www.ececs.uc.edu/~wjone

Articles in Scholarly Journals [Incomplete List]

  1. Fault Modeling and Detection for Drowsy SRAM Caches
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 6, pp. 1084–1100, 2007
  2. Testing Analog and Mixed-Signal Circuits With Built-In Hardware—A New Approach
    IEEE Transactions on Instrumentation and Measurement, vol. 56, no. 3, pp. 840–855, 2007
  3. Crosstalk Test Pattern Generation for Dynamic Programmable Logic Arrays
    IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 4, pp. 1288–1302, 2006
  4. Revisiting Response Compaction in Space for Full-Scan Circuits With Nonexhaustive Test Sets Using Concept of Sequence Characterization
    IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 5, pp. 1662–1677, 2005
  5. A Built-In Self-Testing Method for Embedded Multiport Memory Arrays
    IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 5, pp. 1721–1738, 2005
  6. A Dual-Mode Built-in Self-Test Technique for Capacitive MEMS Devices
    IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 5, pp. 1739–1750, 2005
  7. Fault Simulation and Response Compaction in Full Scan Circuits Using HOPE
    IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 6, pp. 2310–2328, 2005
  8. A Parallel Built-In Self-Diagnostic Method for Nontraditional Faults of Embedded Memory Arrays
    IEEE Transactions on Instrumentation and Measurement, vol. 53, no. 4, pp. 915–932, 2004
  9. Embedded core test generation using broadcast test architecture and netlist scrambling
    IEEE Transactions on Reliability, vol. 52, no. 4, pp. 435–443, 2003
  10. Design theory and implementation for low-power segmented bus systems
    ACM Transactions on Design Automation of Electronic Systems, vol. 8, no. 1, pp. 38–54, 2003
  11. An efficient BIST method for non-traditional faults of embedded memory arrays
    IEEE Transactions on Instrumentation and Measurement, vol. 52, no. 5, pp. 1381–1390, 2003
  12. Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets
    IEEE Transactions on Instrumentation and Measurement, vol. 52, no. 5, pp. 1363–1380, 2003
  13. An efficient BIST method for distributed small buffers
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 4, pp. 512–515, 2002
  14. Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering
    IEEE Transactions on Instrumentation and Measurement, vol. 51, no. 1, pp. 150–172, 2002
  15. A parallel built-in self-diagnostic method for embedded memory arrays
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 4, pp. 449–465, 2002
  16. A parallel transparent BIST method for embedded memory arrays by tolerating redundant operations
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 5, pp. 617–628, 2002
  17. Charge-sharing alleviation and detection for CMOS domino circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 266–280, 2001
  18. An adaptive path selection method for delay testing
    IEEE Transactions on Instrumentation and Measurement, vol. 50, no. 5, pp. 1109–1118, 2001
  19. Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities
    IEEE Transactions on Instrumentation and Measurement, vol. 50, no. 6, pp. 1725–1747, 2001
  20. Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis
    VLSI Design, vol. 12, no. 4, pp. 457–474, 2001
  21. Random Pattern Testability Enhancement by Circuit Rewiring
    VLSI Design, vol. 12, no. 4, pp. 537–549, 2001
  22. Low-speed scan testing of charge-sharing faults for CMOS domino circuits
    Electronics Letters, vol. 36, no. 20, p. 1684, 2000
  23. Reducing test application time by scan flip-flops sharing
    IEE Proceedings - Computers and Digital Techniques, vol. 147, no. 1, p. 42, 2000
  24. Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
    IEE Proceedings - Computers and Digital Techniques, vol. 147, no. 5, p. 343, 2000
  25. TAIR: testability analysis by implication reasoning
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 1, pp. 152–160, 2000
  26. Segmented bus design for low-power systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 1, pp. 25–29, 1999
  27. Confidence analysis for defect-level estimation of VLSI random testing
    ACM Transactions on Design Automation of Electronic Systems, vol. 3, no. 3, pp. 389–407, 1998
  28. Syndrome Signature in Output Compaction for VLSI Built-in Self-Test
    VLSI Design, vol. 7, no. 2, pp. 191–201, 1998
  29. Journal of Electronic Testing, vol. 11, no. 2, pp. 131–146, 1997
  30. Pseudorandom test-length analysis using differential solutions
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 7, pp. 815–825, 1996
  31. PGEN: A Novel Approach to Sequential Circuit Test Generation
    VLSI Design, vol. 4, no. 3, pp. 149–165, 1996
  32. Realizing a high measure of confidence for defect level analysis of random testing [VLSI]
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, no. 3, pp. 446–450, 1995
  33. A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 3, pp. 374–384, 1995
  34. Timing optimization by gate resizing and critical path identification
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 2, pp. 201–217, 1995
  35. On testing of sequential machines using circuit decomposition and stochastic modeling
    IEEE Transactions on Systems, Man, and Cybernetics, vol. 25, no. 3, pp. 489–504, 1995
  36. CACOP-a random pattern testability analyzer
    IEEE Transactions on Systems, Man, and Cybernetics, vol. 25, no. 5, pp. 865–871, 1995
  37. Defect level estimation of circuit testing using sequential statistical analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 2, pp. 336–348, 1993
  38. Analysis of Hamming count compaction scheme
    Journal of Electronic Testing, vol. 2, no. 4, pp. 373–384, 1991
  39. Multiple-output parity bit signature for exhaustive testing
    Journal of Electronic Testing, vol. 1, no. 2, pp. 175–178, 1990
  40. Probabilistic modeling and fault analysis in sequential logic using computer simulation
    IEEE Transactions on Systems, Man, and Cybernetics, vol. 20, no. 2, pp. 490–498, 1990
  41. PROBABILISTIC FAULT LOCATION IN COMBINATIONAL LOGIC NETWORK USING CONCEPTS OF FAULT DISTANCE AND INPUT FEATURE
    Cybernetics and Systems, vol. 20, no. 5, pp. 385–399, 1989
  42. Further studies on the matrix approach to the measurement and control problems of synchronous sequential machines— Performance evaluation by computer simulation and application of specific heuristics
    Computers & Electrical Engineering, vol. 12, no. 3-4, pp. 161–173, 1986
  43. MODIFIED TRANSITION MATRIX AND FAULT TESTING IN SEQUENTIAL LOGIC CIRCUITS UNDER RANDOM STIMULI WITH A SPECIFIED MEASURE OF CONFIDENCE
    Cybernetics and Systems, vol. 17, no. 1, pp. 1–12, 1986