Articles in Scholarly Journals [Incomplete List]

1. Fast- Frequency Offset Cancellation Loop Using Low-IF Receiver and Fractional-N PLL
   IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 3, pp. 272–276, 2007
2. Temperature-Aware Placement for SOCs
   Proceedings of the IEEE, vol. 94, no. 8, pp. 1502–1518, 2006
3. A 32-bit carry lookahead adder using dual-path all-N logic
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 992–996, 2005
4. Gate leakage tolerant circuits in deep sub-100 nm CMOS technologies
   Smart Materials and Structures, vol. 15, no. 1, pp. S21–S28, 2005
5. Design of ESD Power Protection With Diode Structures for Mixed-Power Supply Systems
   IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 260–264, 2004
6. Reduced-Order Modeling of Weakly Nonlinear MEMS Devices With Taylor-Series Expansion and Arnoldi Approach
   Journal of Microelectromechanical Systems, vol. 13, no. 3, pp. 441–451, 2004
7. Chip-level charged-device modeling and simulation in CMOS integrated circuits
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 1, pp. 67–81, 2003
8. Timing constraints for domino logic gates with timing-dependent keepers
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 1, pp. 96–103, 2003
9. Energy-efficient skewed static logic with dual Vt: design and synthesis
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, pp. 64–70, 2003
10. Noise-aware interconnect power optimization in domino logic synthesis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, pp. 79–89, 2003
11. Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 5, pp. 879–887, 2003
12. Minimum delay optimization for domino logic circuits---a coupling-aware approach
    ACM Transactions on Design Automation of Electronic Systems, vol. 8, no. 2, pp. 203–213, 2003
13. Noise constrained transistor sizing and power optimization for dual V/sub t/ domino logic
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 5, pp. 532–541, 2002
14. High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 6, pp. 434–439, 2002
15. High performance dynamic logic incorporating gate voltage controlled keeper structure for wide fan-in gates
    Electronics Letters, vol. 38, no. 16, p. 852, 2002
16. Differential pass-transistor clocked flipflop
    Electronics Letters, vol. 37, no. 12, p. 732, 2001
17. Effects of Crank Length on the Dynamics Behavior of a Flexible Connecting Rod
    Journal of Vibration and Acoustics, vol. 123, no. 3, p. 318, 2001
18. Low-power adiabatic computing with NMOS energy recovery logic
    Electronics Letters, vol. 36, no. 16, p. 1349, 2000
19. EXODUS: Inter-module bus-encoding scheme for system-on-a-chip
    Electronics Letters, vol. 36, no. 7, p. 615, 2000
20. Modular charge recycling pass transistor logic (MCRPL)
    Electronics Letters, vol. 36, no. 5, p. 404, 2000
21. Cell-level placement for improving substrate thermal distribution
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 2, pp. 253–266, 2000
22. Interconnect thermal modeling for accurate simulation of circuit timing and reliability
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 2, pp. 197–205, 2000
23. Interconnect simulation in a fast timing simulator ILLIADS-I
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 46, no. 1, pp. 178–189, 1999
24. Optical 2R remodulator using feedforward control of semiconductor optical amplifier gain
    Microwave and Optical Technology Letters, vol. 21, no. 1, pp. 39–42, 1999
25. Improved domino structures effective for high performance design
    Electronics Letters, vol. 35, no. 5, p. 367, 1999
26. ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 8, pp. 668–681, 1998
27. Matrix unit cell scheduler (MUCS) for input-buffered ATM switches
    IEEE Communications Letters, vol. 2, no. 1, pp. 20–23, 1998
28. A study of hot-carrier-induced mismatch drift: a reliability issue for VLSI circuits
    IEEE Journal of Solid-State Circuits, vol. 33, no. 6, pp. 921–927, 1998
29. Average power analysis of sequential circuits using an autoregressive model
    Circuits, Systems, and Signal Processing, vol. 17, no. 2, pp. 289–304, 1998
30. Analog Integrated Circuits and Signal Processing, vol. 17, no. 1/2, pp. 51–65, 1998
31. Statistical estimation of average power dissipation using nonparametric techniques
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 1, pp. 65–73, 1998
32. Rate-equation-based laser models with a single solution regime
    Journal of Lightwave Technology, vol. 15, no. 4, pp. 717–730, 1997
33. iTEM: a temperature-dependent electromigration reliability diagnosis tool
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 8, pp. 882–893, 1997
34. Analog Integrated Circuits and Signal Processing, vol. 14, no. 1/2, pp. 81–90, 1997
35. Determining accuracy bounds for simulation-based switching activity estimation
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 6, pp. 611–618, 1996
36. Scalable optoelectronic ATM networks: the iPOINT fully functional testbed
    Journal of Lightwave Technology, vol. 13, no. 6, pp. 1093–1103, 1995
37. An accurate intrinsic capacitance modeling for deep submicrometer MOSFET's
    IEEE Transactions on Electron Devices, vol. 42, no. 3, pp. 540–548, 1995
38. Improvements to the standard theory for photoreceiver noise
    Journal of Lightwave Technology, vol. 12, no. 7, pp. 1174–1184, 1994
39. Simulation of electrical overstress thermal failures in integrated circuits
    IEEE Transactions on Electron Devices, vol. 41, no. 3, pp. 359–366, 1994
40. Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 4, pp. 482–493, 1994
41. An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 11, pp. 1621–1634, 1993
42. Modeling and simulation of hot-carrier-induced device degradation in MOS circuits
    IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 585–595, 1993
43. A MODFET-based optoelectronic integrated circuit receiver for optical interconnects
    IEEE Transactions on Electron Devices, vol. 40, no. 8, pp. 1406–1416, 1993
44. Electrical overstress (EOS) power profiles: A guideline to qualify EOS hardness of semiconductor devices
    Journal of Electrostatics, vol. 31, no. 2-3, pp. 161–176, 1993
45. The engineering research center for compound semiconductor microelectronics
    Proceedings of the IEEE, vol. 81, no. 1, pp. 132–151, 1993
46. Computationally efficient simulation of a lossy transmission line with skin effect by using numerical inversion of Laplace transform
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 39, no. 11, pp. 861–868, 1992
47. Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 2, pp. 235–246, 1992
48. A high-performance AlGaAs/InGaAs/GaAs pseudomorphic MODFET-based monolithic optoelectronic receiver
    IEEE Photonics Technology Letters, vol. 4, no. 1, pp. 73–76, 1992
49. An accurate analytical delay model for BiCMOS driver circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 5, pp. 577–588, 1991
50. Improved net merging method for gate matrix layout
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 9, pp. 947–951, 1988