Salvatore Pontarelli received the Laurea degree in electronic engineering from the University of Bologna, Bologna, Italy in 1999 and the Ph.D. degree in microelectronics and telecommunications engineering from the University of Rome "Tor Vergata", Rome, Italy in 2003. Currently he has a postdoctoral fellowship with the Department of Electronic Engineering of the University of Rome "Tor Vergata". His research interests are fault tolerance, error correction codes, reconfigurable digital architectures, QCA (quantum dot cellular automata), and use of FPGA for accelerate networking application. Pontarelli is or has been a TPC Member of IEEE Symposium on Defect and Fault Tolerance in VLSI systems, IEEE International Conference on Computer Design (ICCD), Logic and Circuit Design Track, and IEEE Southern Programmable Logic Conference (SPL). He is reviewer for IEEE Transactions on Computers, IEEE Transactions on Dependable and Secure Computing, IEEE Transactions on Nanotechnology, IET Circuits, Devices & Systems, IET Electronics Letter, Integration, the VLSI Journal, Elsevier, and Journal of Electronic Testing: Theory and applications, Elsevier.
Biography Updated on 11 May 2011