Reiner Hartenstein

Reiner Hartenstein is currently a Professor of CS&E at TU Kaiserslautern. He received all his academic degrees from the Electrical Engineering Department at Karlsruhe University, where he later became an Associate Professor of Computer Science. Before joining Kaiserslautern, he has worked in character recognition, image processing, computer architecture, microprogramming, and hardware description languages. At Kaiserslautern he worked on computer structures, high-level hardware description languages, and on VLSI design methods and tools. In 1983 he was founder of the German Mead-&-Conway-style German multiuniversity E.I.S. project. Since about 20 years, he has worked on reconfigurable computing and related compilation techniques. The achievements of his group have been supported by various funding agencies. During the 1980s the EU has spent more than 100 million $ for an international consortium developing a VLSI CAD framework around his hardware language KARL. Professor Hartenstein, IEEE fellow, SDPS fellow, and FPL fellow, has organized numerous international conferences and has founded 2 succesful international conference series. Many times Professor Hartenstein has been invited to international conferences as an invited speaker, keynote speaker, embedded tutorial speaker, and as a panelist. He has authored, coauthored, or coedited 14 books and more than 400 papers.

Biography Updated on 11 September 2007

Personal Home Page

http://hartenstein.de

Articles in Scholarly Journals [Incomplete List]

  1. Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic
    ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 2, pp. 251–281, 2006
  2. Configware and morphware going mainstream
    Journal of Systems Architecture, vol. 49, no. 4-6, pp. 127–142, 2003
  3. Applying ELAN Strategies in Simulating Processors over Simple Architectures
    Electronic Notes in Theoretical Computer Science, vol. 70, no. 6, pp. 84–99, 2002
  4. Seeking solutions in configurable computing
    Computer, vol. 30, no. 12, pp. 38–43, 1997
  5. High-performance computing using a reconfigurable accelerator
    Concurrency: Practice and Experience, vol. 8, no. 6, pp. 429–443, 1996
  6. CMOS interconnect modelling for timing analysis
    Microprocessing and Microprogramming, vol. 37, no. 1-5, pp. 7–10, 1993
  7. A novel ASIC design approach based on a new machine paradigm
    IEEE Journal of Solid-State Circuits, vol. 26, no. 7, pp. 975–989, 1991
  8. Explicit fault modeling and hierarchical test pattern generation in the KARATE system
    Microprocessing and Microprogramming, vol. 27, no. 1-5, pp. 675–680, 1989
  9. Synthesis of systolic architectures using the SYS3 system
    Microprocessing and Microprogramming, vol. 27, no. 1-5, pp. 479–486, 1989
  10. A technology description method for generalized layout / circuit relations
    Microprocessing and Microprogramming, vol. 23, no. 1-5, pp. 15–20, 1988
  11. MLED: A multiple abstraction level graphical editor
    Microprocessing and Microprogramming, vol. 21, no. 1-5, pp. 585–590, 1987
  12. A flexible architecture for image processing
    Microprocessing and Microprogramming, vol. 21, no. 1-5, pp. 65–71, 1987
  13. Research and development in microprogramming, microprocessors and related fields in the F.R. Germany
    Euromicro Newsletter, vol. 5, no. 3, pp. 121–124, 1979