Zoran Salcic

Zoran Salcic is a Professor of computer systems engineering at the University of Auckland, New Zealand. He holds the B.E., M.E., and Ph.D. degrees in electrical and computer engineering from the University of Sarajevo received in 1972, 1974, and 1976, respectively. He did most of the Ph.D. research at the City University New York in 1974 and 1975. He has been with the academia since 1972, with the exception of years 1985–1990 when he took the posts in the industrial establishment, leading a major industrial enterprise institute in the area of computer engineering. His expertise spans the whole range of disciplines within computer systems engineering: complex digital systems design, custom-computing machines, reconfigurable systems, field-programmable gate arrays, processor and computer systems architecture, embedded systems and their implementation, design automation tools for embedded systems, hardware/software co-design, new computing architectures and models of computation for heterogeneous embedded systems, and related areas. He has published more than 180 refereed journal and conference papers and numerous technical reports.

Biography Updated on 12 July 2006

Articles in Scholarly Journals [Incomplete List]

  1. A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems
    Applied Soft Computing, vol. 7, no. 3, pp. 979–994, 2007
  2. Supporting Symmetric 128-bit AES in Networked Embedded Systems: An Elliptic Curve Key Establishment Protocol-on-Chip
    EURASIP Journal on Embedded Systems, vol. 2007, Article ID 65751, 9 pages, 2007
  3. A Floating-Point FPGA-Based Self-Tuning Regulator
    IEEE Transactions on Industrial Electronics, vol. 53, no. 2, pp. 693–704, 2006
  4. A Comparison of Accuracy Using a GPS and a Low-Cost DGPS
    IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 5, pp. 1677–1683, 2006
  5. Modeling Embedded Systems: From SystemC and Esterel to DFCharts
    IEEE Design and Test of Computers, vol. 23, no. 5, pp. 348–358, 2006
  6. HiDRAâ??A reactive multiprocessor architecture for heterogeneous embedded systems
    Microprocessors and Microsystems, vol. 30, no. 2, pp. 72–85, 2006
  7. FPGA Prototyping of RNN Decoder for Convolutional Codes
    EURASIP Journal on Applied Signal Processing, vol. 2006, Article ID 15640, 9 pages, 2006
  8. A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study
    EURASIP Journal on Applied Signal Processing, vol. 2006, Article ID 89186, 12 pages, 2006
  9. Customizing Multiprocessor Implementation of an Automated Video Surveillance System
    EURASIP Journal on Embedded Systems, vol. 2006, Article ID 45758, 12 pages, 2006
  10. Theory and application of neural networks for / rate convolutional decoders
    Engineering Applications of Artificial Intelligence, vol. 18, no. 8, pp. 931–949, 2005
  11. International Journal of Software Engineering and Knowledge Engineering, vol. 15, no. 2, p. 405, 2005
  12. Prototyping Neuroadaptive Smart Antenna for 3G Wireless Communications
    EURASIP Journal on Applied Signal Processing, vol. 2005, no. 7, pp. 1093–1109, 2005
  13. REFLIX: a processor core with native support for control-dominated embedded applications
    Microprocessors and Microsystems, vol. 28, no. 1, pp. 13–25, 2004
  14. ISDE?an integrated systems development environment for custom-computing machines implemented in FPLDs
    Microprocessors and Microsystems, vol. 25, no. 9-10, pp. 427–435, 2002
  15. FPGA-based adaptive tracking estimation computer
    IEEE Transactions on Aerospace and Electronic Systems, vol. 37, no. 2, pp. 699–706, 2001
  16. A Real-Time Implementation of Nonlinear Unsharp Masking with FPLDs
    Real-Time Imaging, vol. 7, no. 2, pp. 195–202, 2001
  17. Wireless Personal Communications, vol. 19, no. 3, pp. 205–226, 2001
  18. High-speed customizable fuzzy-logic processor: architecture and implementation
    IEEE Transactions on Systems, Man, and Cybernetics - Part A: Systems and Humans, vol. 31, no. 6, pp. 731–737, 2001
  19. Scalar-based direct algorithm mapping FPLD implementation of a Kalman filter
    IEEE Transactions on Aerospace and Electronic Systems, vol. 36, no. 3, pp. 879–888, 2000
  20. A new method for instantaneous power system frequency measurement using reference points detection
    Electric Power Systems Research, vol. 55, no. 2, pp. 97–102, 2000
  21. Wireless Personal Communications, vol. 14, no. 3, pp. 235–254, 2000
  22. RAPROS—A rapid prototyping system and run-time environment for PC-based hardware/software applications
    Microprocessors and Microsystems, vol. 22, no. 9, pp. 543–552, 1999
  23. FLIX environment for generation of custom-configurable machines in FPLDs for embedded applications
    Microprocessors and Microsystems, vol. 23, no. 8-9, pp. 513–526, 1999
  24. IMECO: A Reconfigurable FPGA-based Image Enhancement Co-Processor Framework
    Real-Time Imaging, vol. 5, no. 6, pp. 385–395, 1999
  25. A comparison of frequency measurement methods for underfrequency load shedding
    Electric Power Systems Research, vol. 45, no. 3, pp. 209–219, 1998
  26. K-FLIX—a framework for custom-configurable embedded Kalman filter microcomputers
    Microprocessors and Microsystems, vol. 22, no. 2, pp. 79–86, 1998
  27. PROTOS— A microcontroller/FPGA-based prototyping system for embedded applications
    Microprocessors and Microsystems, vol. 21, no. 4, pp. 249–256, 1997