Maurizio Palesi

Maurizio Palesi received the M.S. and Ph.D. degrees in computer engineering from the University of Catania, Italy, in 1999 and 2003, respectively. Since November 2010 he is Assistant Professor at Kore University, Italy. Dr. Palesi serves on the Editorial Board of VLSI Design journal as an Associate Editor since May 2007. He has served as a Guest Editor for the VLSI Design Journal, the International Journal of High Performance Systems Architecture, Elsevier MICPRO Journal and ACM Transactions on Embedded Computing Systems. He is in the Technical Program Committee of several IEEE/ACM International Conferences including DATE, RTAS, CODES+ISSS, ESTIMedia, NOCS, SOCC, VLSI, ISC, and SITIS. He has been co-organizer of the four editions of the International Workshop on Network-on-Chip Architectures (from 2008 to 2011). Dr. Palesi is member of the European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC).

Biography Updated on 16 June 2013

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