Massimo Poncino

Personal Home Page

http://www2.polito.it/ricerca/eda/cv_poncino.html

Articles in Scholarly Journals [Incomplete List]

  1. SystemC co-simulation for core-based embedded systems
    Design Automation for Embedded Systems, vol. 11, no. 2-3, pp. 141–166, 2007
  2. Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support
    IEEE Transactions on Computers, vol. 56, no. 5, pp. 606–621, 2007
  3. Low-energy RGB color approximation for digital LCD interfaces
    IEEE Transactions on Consumer Electronics, vol. 52, no. 3, pp. 1004–1012, 2006
  4. Reducing Conflict Misses by Application-Specific Reconfigurable Indexing
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2626–2637, 2006
  5. Energy-efficient bus encoding for LCD digital display interfaces
    IEEE Transactions on Consumer Electronics, vol. 51, no. 2, pp. 624–634, 2005
  6. Book review of Ships and the Development of Maritime Technology in the Indian Ocean, edited by D. Parkin and R. Barnes (London; New York: Routledge Curzon, 2002), pp. 360 [AQ2]. £55.00. ISBN 0 7007 1235 6
    Maritime Policy & Management, vol. 30, no. 2, pp. 191–191, 2003
  7. Systemc cosimulation and emulation of multiprocessor soc designs
    Computer, vol. 36, no. 4, pp. 53–59, 2003
  8. Discharge current steering for battery lifetime optimization
    IEEE Transactions on Computers, vol. 52, no. 8, pp. 985–995, 2003
  9. Scheduling battery usage in mobile systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1136–1143, 2003
  10. Minimizing memory access energy in embedded systems by selective instruction compression
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 5, pp. 521–531, 2002
  11. Layout-driven memory synthesis for embedded systems-on-chip
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 2, pp. 96–105, 2002
  12. Stream synthesis for efficient power simulation based on spectral transforms
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 3, pp. 417–426, 2001
  13. Discrete-time battery models for system-level low-power design
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 5, pp. 630–640, 2001
  14. Parameterized RTL power models for soft macros
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 6, pp. 880–887, 2001
  15. Synthesis of power-managed sequential components based on computational kernel extraction
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp. 1118–1131, 2001
  16. A multilevel engine for fast power simulation of realistic input streams
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 4, pp. 459–472, 2000
  17. Symbolic optimization of interacting controllers based on redundancy identification and removal
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 7, pp. 760–772, 2000
  18. Architectures and synthesis algorithms for power-efficient bus interfaces
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 9, pp. 969–980, 2000
  19. Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation
    IEEE Design & Test of Computers, vol. 17, no. 2, pp. 74–85, 2000
  20. Glitch power minimization by selective gate freezing
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 3, pp. 287–298, 2000
  21. Automatic selection of instruction op-codes of low-power core processors
    IEE Proceedings - Computers and Digital Techniques, vol. 146, no. 4, p. 173, 1999
  22. Application of symbolic FSM Markovian analysis to protocol verification
    IEE Proceedings - Computers and Digital Techniques, vol. 146, no. 5, p. 221, 1999
  23. Automatic synthesis of easily scalable bus arbiters with dynamic priority assignment strategies
    Computers & Electrical Engineering, vol. 24, no. 3-4, pp. 223–228, 1998
  24. Telescopic units: a new paradigm for performance optimization of VLSI designs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 3, pp. 220–232, 1998
  25. Power optimization of core-based systems by address bus encoding
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 4, pp. 554–562, 1998
  26. Cellular-automata models for reliability analysis of systems on silicon
    IEEE Transactions on Reliability, vol. 46, no. 2, pp. 173–183, 1997
  27. Testing core-based systems: a symbolic methodology
    IEEE Design & Test of Computers, vol. 14, no. 4, pp. 69–77, 1997
  28. An application of hopfield networks to worst-case power analysis of RT-level VLSI systems
    International Journal of Engineering Science, vol. 35, no. 8, pp. 783–792, 1997
  29. Automatic state space decomposition for approximate FSM traversal based on circuit analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 12, pp. 1451–1464, 1996
  30. Using connectivity and spectral methods to characterize the structure of sequential logic circuits
    Microprocessing and Microprogramming, vol. 41, no. 7, pp. 487–500, 1995
  31. The impact of cell library characteristics on area, speed and power consumption of CMOS circuits
    International Journal of Electronics, vol. 78, no. 2, pp. 395–407, 1995
  32. Modelling sequential circuits with cellular automata
    International Journal of Systems Science, vol. 26, no. 7, pp. 1415–1428, 1995
  33. A study of the resetability of synchronous sequential circuits
    Microprocessing and Microprogramming, vol. 38, no. 1-5, pp. 395–402, 1993