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Articles in Scholarly Journals [Incomplete List]

1. Partitioning-based decoupling capacitor budgeting via sequence of linear programming?
   Integration, the VLSI Journal, vol. 40, no. 4, pp. 516–524, 2007
2. Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp. 680–692, 2007
3. TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp. 1382–1392, 2007
4. Power/Ground Network Optimization Considering Decap Leakage Currents
   IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 10, pp. 1012–1016, 2006
5. Symbolic Analysis of Analog Circuits By Boolean Logic Operations
   IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 11, pp. 1313–1317, 2006
6. Wideband Passive Multiport Model Order Reduction and Realization of$RLCM$Circuits
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 8, pp. 1496–1509, 2006
7. Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2402–2412, 2006
8. Fast Thermal Simulation for Runtime Temperature Tracking and Management
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2882–2893, 2006
9. Nonlinear Transient and Distortion Analysis via Frequency Domain Volterra Series
   Circuits, Systems & Signal Processing, vol. 25, no. 3, pp. 295–314, 2006
10. Time-domain analysis methodology for large-scale RLC circuits and its applications
    Science in China Series F: Information Sciences, vol. 49, no. 5, pp. 665–680, 2006
11. A Fast Delay Computation for the Hybrid Structured Clock Network
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 7, pp. 1964–1970, 2005
12. A General Hierarchical Circuit Modeling and Simulation Algorithm
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 418–434, 2005
13. Hierarchical Approach to Exact Symbolic Analysis of Large Analog Circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 8, pp. 1241–1250, 2005
14. Efficient Approximation of Symbolic Expressions for Analog Behavioral Modeling and Analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 6, pp. 907–918, 2004
15. Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 3, pp. 277–284, 2003
16. Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 12, pp. 1678–1684, 2003
17. Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis
    Integration, the VLSI Journal, vol. 34, no. 1-2, pp. 65–86, 2003