Articles in Scholarly Journals [Incomplete List]

1. SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 4, pp. 377–390, 2007
2. Routability of Network Topologies in FPGAs
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 8, pp. 948–951, 2007
3. A framework for modeling and optimization of prescient instruction prefetch
   ACM SIGMETRICS Performance Evaluation Review, vol. 31, no. 1, p. 13, 2003
4. A scheduler ASIC for a programmable packet switch
   IEEE Micro, vol. 20, no. 1, pp. 42–48, 2000
5. International Journal of Parallel Programming, vol. 27, no. 5, pp. 327–356, 1999
6. The design of an SRAM-based field-programmable gate array. I. Architecture
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 2, pp. 191–197, 1999
7. The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 3, pp. 321–330, 1999
8. The Transmogrifier-2: a 1 million gate rapid-prototyping system
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 2, pp. 188–198, 1998
9. Exploiting dual data-memory banks in digital signal processors
   ACM SIGOPS Operating Systems Review, vol. 30, no. 5, pp. 234–243, 1996
10. Exploiting dual data-memory banks in digital signal processors
    ACM SIGPLAN Notices, vol. 31, no. 9, pp. 234–243, 1996
11. Minimizing excess code length and VLSI complexity in the multiplication free approximation of arithmetic coding
    Information Processing & Management, vol. 30, no. 6, pp. 805–816, 1994
12. A multiprocessor architecture for Viterbi decoders with linear speedup
    IEEE Transactions on Signal Processing, vol. 41, no. 9, pp. 2907–2917, 1993
13. The effect of logic block architecture on FPGA performance
    IEEE Journal of Solid-State Circuits, vol. 27, no. 3, pp. 281–287, 1992
14. Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency
    IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1217–1225, 1990
15. MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache
    IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 790–799, 1987
16. A Pipelined Distributed Arithmetic PFFT Processor
    IEEE Transactions on Computers, vol. C-32, no. 12, pp. 1128–1136, 1983