Magdy Bayoumi

Articles in Scholarly Journals [Incomplete List]

  1. A network of sensor-based framework for automated visual surveillance
    Journal of Network and Computer Applications, vol. 30, no. 3, pp. 1244–1271, 2007
  2. Low-Power Cache Design Using 7T SRAM Cell
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 4, pp. 318–322, 2007
  3. Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 3, pp. 338–345, 2007
  4. MAC-SCC: a medium access control protocol with separate control channel for reconfigurable multi-hop wireless networks
    IEEE Transactions on Wireless Communications, vol. 5, no. 7, pp. 1805–1817, 2006
  5. NEDA: A Low-Power High-Performance DCT Architecture
    IEEE Transactions on Signal Processing, vol. 54, no. 3, pp. 955–964, 2006
  6. A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 9, pp. 1153–1163, 2006
  7. Design Methodologies for High-Performance Noise-Tolerant XOR–XNOR Circuits
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 4, pp. 867–878, 2006
  8. Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 12, pp. 1309–1321, 2006
  9. A New Efficient Block-Matching Algorithm for Motion Estimation
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 42, no. 1, pp. 21–33, 2006
  10. Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 40, no. 3, pp. 355–369, 2005
  11. Autonomous Decentralized Systems Based Approach to Object Detection in Sensor Clusters
    IEICE Transactions on Communications, vol. E88-B, no. 12, pp. 4462–4469, 2005
  12. Noise Metrics in Flip-Flop Designs
    IEICE Transactions on Information and Systems, vol. E88-D, no. 7, pp. 1501–1505, 2005
  13. Leakage sources and possible solutions in nanometer CMOS technologies
    IEEE Circuits and Systems Magazine, vol. 5, no. 4, pp. 6–17, 2005
  14. Journal of Circuits, Systems, and Computers, vol. 14, no. 4, p. 735, 2005
  15. Editorial
    EURASIP Journal on Applied Signal Processing, vol. 2005, no. 7, pp. 989–992, 2005
  16. Efficient Shield Insertion for Inductive Noise Reduction in Nanometer Technologies
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 3, pp. 401–405, 2005
  17. High-Performance and Low-Power Conditional Discharge Flip-Flop
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5, pp. 477–484, 2004
  18. Journal of Circuits, Systems, and Computers, vol. 13, no. 6, p. 1271, 2004
  19. A methodology for low power scheduling with resources operating at multiple voltages
    Integration, the VLSI Journal, vol. 37, no. 1, pp. 29–62, 2004
  20. A Low Power Architecture for HASM Motion Tracking
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 37, no. 1, pp. 111–127, 2004
  21. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 35, no. 2, pp. 155–178, 2003
  22. Interconnect noise analysis and optimization in deep submicron technology
    IEEE Circuits and Systems Magazine, vol. 3, no. 4, pp. 6–17, 2003
  23. Editorial
    EURASIP Journal on Applied Signal Processing, vol. 2003, no. 6, pp. 491–493, 2003
  24. A query on the year of King Wu?s conquest over King Zhou determined by the Xia-Shang-Zhou Chronology Project ??Materials finding and astronomical methods for chronological studies of China
    Science in China Series G, vol. 46, no. 5, p. 481, 2003
  25. Efficient mapping algorithm of multilayer neural network on torus architecture
    IEEE Transactions on Parallel and Distributed Systems, vol. 14, no. 9, pp. 932–943, 2003
  26. A computational kernel for fast and efficient compressed-domain calculations of wavelet subband energies
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 7, pp. 389–392, 2003
  27. Parallel multiplication-free algorithm and architecture for affine-based motion compensation
    Optical Engineering, vol. 42, no. 1, p. 255, 2003
  28. Low power very large scale integration prototype for three-dimensional discrete wavelet transform processor with medical applications
    Journal of Electronic Imaging, vol. 12, no. 2, p. 270, 2003
  29. Three-dimensional discrete wavelet transform architectures
    IEEE Transactions on Signal Processing, vol. 50, no. 8, pp. 2050–2063, 2002
  30. A low power VLSI architecture for mesh-based video motion tracking
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 7, pp. 488–504, 2002
  31. MRI data compression using a 3-D discrete wavelet transform
    IEEE Engineering in Medicine and Biology Magazine, vol. 21, no. 4, pp. 95–103, 2002
  32. The Journal of VLSI Signal Processing, vol. 31, no. 2, pp. 173–184, 2002
  33. Algorithm-based low-power VLSI architecture for 2D mesh video-object motion tracking
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 12, no. 4, pp. 227–237, 2002
  34. Performance analysis of low-power 1-bit CMOS full adder cells
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 1, pp. 20–29, 2002
  35. A novel high-performance CMOS 1-bit full-adder cell
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 5, pp. 478–481, 2000
  36. The blackjack tutor chip
    IEEE Potentials, vol. 18, no. 2, pp. 38–42, 1999
  37. Analog Integrated Circuits and Signal Processing, vol. 18, no. 2/3, pp. 175–194, 1999
  38. The Journal of VLSI Signal Processing, vol. 18, no. 2, pp. 125–140, 1998
  39. Three-dimensional defect sensitivity modeling for open circuits in ULSI structures
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 4, pp. 366–371, 1998
  40. A thinning algorithm for Arabic characters using ART2 neural network
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 2, pp. 260–264, 1998
  41. The extended cube connected cycles: an efficient interconnection for massively parallel systems
    IEEE Transactions on Computers, vol. 45, no. 5, pp. 609–614, 1996
  42. Efficient mapping of ANNs on hypercube massively parallel machines
    IEEE Transactions on Computers, vol. 44, no. 6, pp. 769–779, 1995
  43. A systolic architecture for modulo multiplication
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 42, no. 11, pp. 725–729, 1995
  44. Introduction
    Journal of VLSI Signal Processing, vol. 11, no. 1-2, pp. 5–6, 1995
  45. Tree-based special-purpose Array architectures for neural computing
    Journal of VLSI Signal Processing, vol. 11, no. 3, pp. 245–262, 1995
  46. The hierarchical hypercube: a new interconnection topology for massively parallel systems
    IEEE Transactions on Parallel and Distributed Systems, vol. 5, no. 1, pp. 17–30, 1994
  47. The nature of defect patterns on integrated-circuit wafer maps
    IEEE Transactions on Reliability, vol. 43, no. 1, pp. 22–29, 1994
  48. Fault-current limiter with thyristor-controlled impedance
    IEEE Transactions on Power Delivery, vol. 8, no. 3, pp. 1518–1528, 1993
  49. Defect clustering viewed through generalized Poisson distribution
    IEEE Transactions on Semiconductor Manufacturing, vol. 5, no. 3, pp. 196–206, 1992
  50. Image segmentation on a 2D array by a directed split and merge procedure
    IEEE Transactions on Signal Processing, vol. 40, no. 11, pp. 2804–2813, 1992
  51. Fast and flexible architectures for RNS arithmetic decoding
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 4, pp. 226–235, 1992
  52. VLSI parallel architecture for Kalman filterAn algorithm specific approach
    Journal of VLSI Signal Processing, vol. 4, no. 2-3, pp. 147–163, 1992
  53. VLSI implementation of a systolic database machine for relational algebra and hashing
    Integration, the VLSI Journal, vol. 11, no. 2, pp. 169–190, 1991
  54. A theta (1) algorithm for modulo addition
    IEEE Transactions on Circuits and Systems, vol. 37, no. 5, pp. 628–631, 1990
  55. Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 8, pp. 804–820, 1990
  56. Testing of a NORA CMOS serial-parallel multiplier
    IEEE Journal of Solid-State Circuits, vol. 24, no. 2, pp. 494–503, 1989
  57. An efficient two's complement systolic multiplier for real-time digital signal processing
    IEEE Transactions on Circuits and Systems, vol. 36, no. 11, pp. 1488–1493, 1989
  58. Systematic algorithm mapping for multidimensional systolic arrays
    Journal of Parallel and Distributed Computing, vol. 7, no. 2, pp. 368–382, 1989
  59. A VLSI implementation of residue adders
    IEEE Transactions on Circuits and Systems, vol. 34, no. 3, pp. 284–288, 1987
  60. A look-up table VLSI design methodology for RNS structures used in DSP applications
    IEEE Transactions on Circuits and Systems, vol. 34, no. 6, pp. 604–616, 1987
  61. Lower bounds for VLSI implementation of residue number system architectures
    Integration, the VLSI Journal, vol. 4, no. 3, pp. 263–269, 1986
  62. Hybrid VLSI architecture of FIR filters using residue number systems
    Electronics Letters, vol. 21, no. 8, p. 358, 1985
  63. A VLSI model for residue number system architectures
    Integration, the VLSI Journal, vol. 2, no. 3, pp. 191–211, 1984
  64. Multi-look-up-table module for RNS systems implementation
    Electronics Letters, vol. 20, no. 2, p. 94, 1984
  65. An area-time efficient NMOS adder
    Integration, the VLSI Journal, vol. 1, no. 4, pp. 317–334, 1983