Jarmo Henrik Takala

Jarmo Henrik Takala received his M.S. (with honors) degree in electrical engineering and Dr.Tech. degree in information technology from Tampere University of Technology (TUT), Tampere, Finland, in 1987 and 1999, respectively. From 1992 to 1996, he was a Research Scientist at VTT-Automation, Tampere, Finland. Between 1995 and 1996, he was a Senior Research Engineer at Nokia Research Center, Tampere, Finland. From 1996 to 1999, he was a Researcher at TUT. Currently, he is a Professor of computer engineering at TUT and Head of the Institute of Digital and Computer Systems of TUT. His research interests include circuit techniques, parallel architectures, and design methodologies for digital signal processing systems. Currently, Dr. Takala is a Member of IEEE Signal Processing Society Technical Committee on Design and Implementation of Signal Processing Systems. He is an Associate Editor for the EURASIP Journal on Embedded Systems. Dr. Takala is a Senior Member of the IEEE.

Biography Updated on 26 June 2007

Personal Home Page

http://www.cs.tut.fi/~takala/

Articles in Scholarly Journals [Incomplete List]

  1. Stride Permutation Networks for Array Processors
    The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 49, no. 1, pp. 51–71, 2007
  2. Journal of Systems Architecture, vol. 53, no. 8, pp. 465–465, 2007
  3. Effects of program compression
    Journal of Systems Architecture, vol. 53, no. 10, pp. 679–688, 2007
  4. Dual Antenna Receivers for High Data Rate Terminals
    Wireless Personal Communications, 2007
  5. Embedded Digital Signal Processing Systems
    EURASIP Journal on Embedded Systems, vol. 2007, Article ID 27517, 1 pages, 2007
  6. Application-Specific Instruction Set Processor Implementation of List Sphere Detector
    EURASIP Journal on Embedded Systems, vol. 2007, Article ID 54173, 14 pages, 2007
  7. Discrete cosine and sine transformsâ??regular algorithms and pipeline architectures
    Signal Processing, vol. 86, no. 2, pp. 230–249, 2006
  8. Scalable FFT Processors and Pipelined Butterfly Units
    The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 43, no. 2-3, pp. 113–123, 2006
  9. Systematic Approach for Path Metric Access in Viterbi Decoders
    IEEE Transactions on Communications, vol. 53, no. 5, pp. 755–759, 2005
  10. Position and velocity reliability testing in degraded GPS signal environments
    GPS Solutions, vol. 8, no. 4, pp. 226–237, 2004
  11. Multiple-Symbol Parallel Decoding for Variable Length Codes
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 7, pp. 676–685, 2004
  12. Multistage interconnection networks for parallel viterbi decoders
    IEEE Transactions on Communications, vol. 51, no. 9, pp. 1536–1545, 2003
  13. Weighted dilution of precision as quality measure in satellite positioning
    IEE Proceedings - Radar, Sonar and Navigation, vol. 150, no. 6, p. 430, 2003
  14. Implementing reactive closed-system specifications
    Journal of Network and Computer Applications, vol. 24, no. 2, pp. 101–123, 2001
  15. Constant geometry algorithm for discrete cosine transform
    IEEE Transactions on Signal Processing, vol. 48, no. 6, pp. 1840–1843, 2000
  16. Distance Transform Algorithm for Bit-Serial SIMD Architectures
    Computer Vision and Image Understanding, vol. 74, no. 2, pp. 150–161, 1999
  17. Safety, liveness and real-time in embedded system design
    Journal of Network and Computer Applications, vol. 22, no. 2, pp. 69–89, 1999