Miriam Leeser

Miriam Leeser is a Professor at Northeastern University, Department of Electrical and Computer Engineering. She received her B.S. degree in electrical engineering from Cornell University, and Diploma and Ph.D. degrees in computer science from Cambridge University in England. After completion of her Ph.D., she joined the faculty of Cornell University, Department of Electrical Engineering, as an Assistant Professor. In January, 1996 she joined the faculty of Northeastern University, where she is the Head of the Reconfigurable Computing Laboratory and a Member of the Computer Engineering Research Group and the Center for Communications and Digital Signal Processing. In 1992 she received an NSF Young Investigator Award to conduct research into floating-point arithmetic. Her research interests include hardware description languages, high-level synthesis, computer arithmetic, and reconfigurable computing for signal and image processing applications. She is a Senior Member of the IEEE, and a Member of the ACM.

Biography Updated on 13 July 2006

Articles in Scholarly Journals [Incomplete List]

  1. Vforce: An Extensible Framework for Reconfigurable Supercomputing
    Computer, vol. 40, no. 3, pp. 39–49, 2007
  2. Enabling MPEG-2 Video Playback in Embedded Systems Through Improved Data Cache Efficiency
    IEEE Transactions on Multimedia, vol. 8, no. 1, pp. 81–89, 2006
  3. Field-Programmable Gate Arrays in Embedded Systems
    EURASIP Journal on Embedded Systems, vol. 2006, Article ID 51312, 2 pages, 2006
  4. Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 39, no. 3, pp. 295–311, 2005
  5. Design and analysis of a dynamically reconfigurable three-dimensional FPGA
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 186–196, 2001
  6. HML, a novel hardware description language and its translation to VHDL
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 1, pp. 1–8, 2000
  7. A data-centric approach to high-level synthesis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 11, pp. 1251–1267, 2000
  8. Rothko: a three-dimensional FPGA
    IEEE Design & Test of Computers, vol. 15, no. 1, pp. 16–23, 1998
  9. Division and square root: choosing the right implementation
    IEEE Micro, vol. 17, no. 4, pp. 56–66, 1997
  10. Verifying a logic-synthesis algorithm and implementation: a case study in software verification
    IEEE Transactions on Software Engineering, vol. 21, no. 10, pp. 822–833, 1995
  11. A methodology for efficient hardware verification
    Formal Methods in System Design, vol. 5, no. 1-2, pp. 95–117, 1994
  12. PBS: proven Boolean simplification
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 4, pp. 459–470, 1994
  13. High level synthesis and generating FPGAs with the BEDROC system
    Journal of VLSI Signal Processing, vol. 6, no. 2, pp. 191–214, 1993
  14. High level synthesis and generation FPGAs with the BEDROC system
    Journal of VLSI Signal Processing, vol. 6, no. 3, pp. i–i, 1993
  15. Formally verified synthesis of combinational CMOS circuits
    Integration, the VLSI Journal, vol. 11, no. 3, pp. 235–250, 1991
  16. Reasoning about the function and timing of integrated circuits with interval temporal logic
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 12, pp. 1233–1246, 1989
  17. Automatic determination of signal flow through MOS transistor networks
    Integration, the VLSI Journal, vol. 4, no. 1, pp. 53–63, 1986