Shen-Iuan Liu

Shen-Iuan Liu was born in Keelung, Taiwan, in 1965. He received the B.S. and Ph.D. degrees in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, in 1987 and 1991, respectively. During 1991–1993, he served as a second lieutenant in the Chinese Air Force. During 1991–1994, he was an Associate Professor in the Department of Electronic Engineering, National Taiwan Institute of Technology. He joined the Department of Electrical Engineering, NTU, in 1994, where he has been a Professor since 1998. His research interests are in analog and digital integrated circuits and systems. Liu has served as chair of the IEEE SSCS Taipei Chapter since 2004. He has served as General Chair of the 15th VLSI Design/CAD Symposium, Taiwan, in 2004, and as Program Cochair of the Fourth IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Fukuoka , Japan, 2004. He was the recipient of the Engineering Paper Award from the Chinese Institute of Engineers in 2003, the Young Professor Teaching Award from MXIC Inc., the Research Achievement Award from NTU, and the Outstanding Research Award from National Science Council in 2004. He has served as a technical program committee member for A-SSCC since 2005 and ISSCC since 2006. He was an Associate Editor for IEEE Transactions on Circuits and Systems—II: Express Briefs in 2006-2007. Now, he is an Associate Editor for IEEE Journal of Solid-State Circuits from 2006 and an Associate Editor for IEEE Transactions on Circuits and Systems—I: Regular Papers from 2008. He is a Senior Member of IEEE and a Member of IEICE.

Biography Updated on 22 January 2008

Personal Home Page

http://www2.ee.ntu.edu.tw/~ecl/Professor/Professor.htm

Articles in Scholarly Journals [Incomplete List]

  1. A Multi-Band Burst-Mode Clock and Data Recovery Circuit
    IEICE Transactions on Electronics, vol. E90-C, no. 4, pp. 802–810, 2007
  2. A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB Receivers
    IEEE Journal of Solid-State Circuits, vol. 42, no. 2, pp. 329–339, 2007
  3. A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
    IEEE Journal of Solid-State Circuits, vol. 42, no. 2, pp. 361–373, 2007
  4. A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- $\mu$m CMOS Technology
    IEEE Journal of Solid-State Circuits, vol. 42, no. 6, pp. 1261–1270, 2007
  5. A Time-Constant Calibrated Phase-Locked Loop With a Fast-Locked Time
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 1, pp. 34–37, 2007
  6. An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18-$\mu$m CMOS
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 3, pp. 217–221, 2007
  7. A 62.5–625-MHz Anti-Reset All-Digital Delay-Locked Loop
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 7, pp. 566–570, 2007
  8. Spur-Suppression Techniques for Frequency Synthesizers
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 8, pp. 653–657, 2007
  9. All-Digital Fast-Locked Synchronous Duty-Cycle Corrector
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 12, pp. 1363–1367, 2006
  10. A Spur-Reduction Technique for a 5-GHz Frequency Synthesizer
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 3, pp. 526–533, 2006
  11. A 200-Mbps$sim $2-Gbps Continuous-Rate Clock-and-Data-Recovery Circuit
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 4, pp. 842–847, 2006
  12. A 0.7–2-GHz Self-Calibrated Multiphase Delay-Locked Loop
    IEEE Journal of Solid-State Circuits, vol. 41, no. 5, pp. 1051–1061, 2006
  13. All-Digital Delay-Locked Loop/Pulsewidth-Control Loop With Adjustable Duty Cycles
    IEEE Journal of Solid-State Circuits, vol. 41, no. 6, pp. 1262–1274, 2006
  14. A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit
    IEEE Journal of Solid-State Circuits, vol. 41, no. 6, pp. 1380–1390, 2006
  15. A Calibrated Pulse Generator for Impulse-Radio UWB Applications
    IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2401–2407, 2006
  16. A 1 V Phase Locked Loop with Leakage Compensation in 0.13  m CMOS Technology
    IEICE Transactions on Electronics, vol. E89-C, no. 3, pp. 295–299, 2006
  17. All-Digital Clock Deskew Buffer with Variable Duty Cycles
    IEICE Transactions on Electronics, vol. E89-C, no. 6, pp. 753–760, 2006
  18. A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs
    IEICE Transactions on Electronics, vol. E88-C, no. 6, pp. 1248–1252, 2005
  19. A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
    IEICE Transactions on Electronics, vol. E88-C, no. 8, pp. 1726–1730, 2005
  20. CMOS Differential-Mode Exponential Voltage-To-Current Converter
    Analog Integrated Circuits and Signal Processing, vol. 45, no. 2, pp. 163–168, 2005
  21. CMOS Wideband Amplifiers Using Multiple Inductive-Series Peaking Technique
    IEEE Journal of Solid-State Circuits, vol. 40, no. 2, pp. 548–552, 2005
  22. A Wide-Range and Fast-Locking All-Digital Cycle-Controlled Delay-Locked Loop
    IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 661–670, 2005
  23. A Single-Path Pulsewidth Control Loop With a Built-In Delay-Locked Loop
    IEEE Journal of Solid-State Circuits, vol. 40, no. 5, pp. 1130–1135, 2005
  24. CMOS Current-Mode Divider and Its Applications
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, no. 3, pp. 145–148, 2005
  25. Selective Metal Parallel Shunting Inductor and Its VCO Application
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 9, pp. 1811–1818, 2005
  26. Magnetic-to-Digital Converters Using Single-Amplifier-Based Second-Order Delta–Sigma Modulators
    IEEE Sensors Journal, vol. 4, no. 2, pp. 226–231, 2004
  27. A 500-MHz–1.25-GHz Fast-Locking Pulsewidth Control Loop With Presettable Duty Cycle
    IEEE Journal of Solid-State Circuits, vol. 39, no. 3, pp. 463–468, 2004
  28. A Low Voltage-Power 13-Bit 16 MSPS CMOS Pipelined ADC
    IEEE Journal of Solid-State Circuits, vol. 39, no. 5, pp. 834–836, 2004
  29. A 3.125-Gb/s Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet
    IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1356–1360, 2004
  30. A 1-V 10.7-MHz Fourth-Order Bandpass<tex>$DeltaSigma$</tex>Modulators Using Two Switched Opamps
    IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp. 2041–2045, 2004
  31. Low Jitter and Multirate Clock and Data Recovery Circuit Using a MSADLL for Chip-to-Chip Interconnection
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 12, pp. 2356–2364, 2004
  32. A Mixed-Mode Synchronous Mirror Delay Insensitive to Supply and Load Variations
    Analog Integrated Circuits and Signal Processing, vol. 39, no. 1, pp. 75–80, 2004
  33. A 1.5 V 12-bit 16 MSPS CMOS Pipelined ADC with 68 dB Dynamic Range
    Analog Integrated Circuits and Signal Processing, vol. 41, no. 2/3, pp. 269–278, 2004
  34. Analog Integrated Circuits and Signal Processing, vol. 37, no. 3, pp. 179–189, 2003
  35. CMOS exponential function generator
    Electronics Letters, vol. 39, no. 1, p. 1, 2003
  36. A fast locking and low jitter delay-locked loop using DHDL
    IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 343–346, 2003
  37. A spread-spectrum clock generator with triangular modulation
    IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 673–676, 2003
  38. Analysis of on-chip spiral inductors using the distributed capacitance model
    IEEE Journal of Solid-State Circuits, vol. 38, no. 6, pp. 1040–1044, 2003
  39. CMOS magnetic field to frequency converter
    IEEE Sensors Journal, vol. 3, no. 2, pp. 241–245, 2003
  40. A wide-range delay-locked loop with a fixed latency of one clock cycle
    IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 1021–1027, 2002
  41. Miniature 3-D inductors in standard CMOS process
    IEEE Journal of Solid-State Circuits, vol. 37, no. 4, pp. 471–480, 2002
  42. Analog Integrated Circuits and Signal Processing, vol. 32, no. 2, pp. 123–134, 2002
  43. Analog Integrated Circuits and Signal Processing, vol. 33, no. 3, pp. 289–300, 2002
  44. 2.4 GHz offset-cancelling down-conversion mixer
    Electronics Letters, vol. 38, no. 9, p. 395, 2002
  45. CCII-based linear transformation elliptic filters
    International Journal of Electronics, vol. 89, no. 2, pp. 123–133, 2002
  46. Pipeline direct digital frequency synthesiser using decomposition method
    IEE Proceedings - Circuits, Devices and Systems, vol. 148, no. 3, p. 141, 2001
  47. Analog Integrated Circuits and Signal Processing, vol. 26, no. 2, pp. 125–128, 2001
  48. Low-voltage CMOS low-noise amplifier using planar-interleaved transformer
    Electronics Letters, vol. 37, no. 8, p. 497, 2001
  49. An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique
    IEEE Journal of Solid-State Circuits, vol. 36, no. 1, pp. 122–128, 2001
  50. A fast-lock mixed-mode DLL using a 2-b SAR algorithm
    IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1464–1471, 2001
  51. A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme
    IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1498–1505, 2001
  52. CMOS oversampling ?S magnetic-to-digital converters
    IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1582–1586, 2001
  53. Low-voltage CMOS frequency synthesizer for ERMES pager application
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 9, pp. 826–834, 2001
  54. A CMOS pulse-shrinking delay element for time interval measurement
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 9, pp. 954–958, 2000
  55. Pseudo-exponential function for MOSFETs in saturation
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 11, pp. 1318–1321, 2000
  56. Realisation of exponential V-I converter using composite NMOS transistors
    Electronics Letters, vol. 36, no. 1, p. 8, 2000
  57. Current-mode pseudo-exponential circuit with tunable input range
    Electronics Letters, vol. 36, no. 16, p. 1335, 2000
  58. Current-mode full-wave rectifier and vector summation circuit
    Electronics Letters, vol. 36, no. 19, p. 1599, 2000
  59. A double-sampling pseudo-two-path bandpass ?S modulator
    IEEE Journal of Solid-State Circuits, vol. 35, no. 2, pp. 276–280, 2000
  60. Clock-deskew buffer using a SAR-controlled delay-locked loop
    IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1128–1136, 2000
  61. A 900-MHz 1-V CMOS frequency synthesizer
    IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1211–1214, 2000
  62. Fast-switching frequency synthesizer with a discriminator-aided phase detector
    IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1445–1452, 2000
  63. Analogue BiCMOS squarer and its applications
    Electronics Letters, vol. 35, no. 5, p. 361, 1999
  64. Dual-input RC integrator and differentiator with tuneable time constants using current feedback amplifiers
    Electronics Letters, vol. 35, no. 22, p. 1910, 1999
  65. Analog Integrated Circuits and Signal Processing, vol. 20, no. 1, pp. 25–29, 1999
  66. Low-voltage BiCMOS four-quadrant multiplier using triode-region transistors
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 46, no. 7, pp. 861–864, 1999
  67. SPICE macro model for MAGFET and its applications
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 4, pp. 370–375, 1999
  68. Low-power clock-deskew buffer for high-speed digital circuits
    IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 554–558, 1999
  69. New dynamic flip-flops for high-speed dual-modulus prescaler
    IEEE Journal of Solid-State Circuits, vol. 33, no. 10, pp. 1568–1571, 1998
  70. Weak inversion four-quadrant multiplier and two-quadrant divider
    Electronics Letters, vol. 34, no. 22, p. 2079, 1998
  71. High-input impedance filters using FTFNs
    International Journal of Electronics, vol. 84, no. 6, pp. 595–598, 1998
  72. Realization of current-mode filters using single FTFN
    International Journal of Electronics, vol. 82, no. 5, pp. 499–502, 1997
  73. Voltage-mode universal filters using two current conveyors
    International Journal of Electronics, vol. 82, no. 2, pp. 145–150, 1997
  74. Low-voltage CMOS four-quadrant multiplier
    Electronics Letters, vol. 33, no. 3, p. 207, 1997
  75. Highly accurate cyclic CMOS time-to-digital converter with extremely low power consumption
    Electronics Letters, vol. 33, no. 10, p. 858, 1997
  76. Single-resistance-controlled sinusoidal oscillator using two FTFNs
    Electronics Letters, vol. 33, no. 14, p. 1185, 1997
  77. High-speed divide-by-4/5 counter for a dual-modulus prescaler
    Electronics Letters, vol. 33, no. 20, p. 1691, 1997
  78. Insensitive current/voltage-mode filters using FTFNs
    Electronics Letters, vol. 32, no. 12, p. 1079, 1996
  79. Table-based log-domain linear transformation filter
    Electronics Letters, vol. 32, no. 19, p. 1771, 1996
  80. Higher-order immittance function synthesis using CCIIIs
    Electronics Letters, vol. 32, no. 25, p. 2295, 1996
  81. Current-mode quadrature sinusoidal oscillator using single FTFN
    International Journal of Electronics, vol. 81, no. 2, pp. 171–175, 1996
  82. A simple and accurate method to measure the threshold voltage of a MOSFET using an MOS active attenuator
    International Journal of Electronics, vol. 81, no. 1, pp. 49–58, 1996
  83. Single-resistance-controlled sinusoidal oscillator using current-feedback amplifiers
    International Journal of Electronics, vol. 80, no. 5, pp. 661–664, 1996
  84. A CMOS square-law vector summation circuit
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, no. 7, pp. 520–523, 1996
  85. New current mode biquad filters using current followers
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 42, no. 7, pp. 380–383, 1995
  86. CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs
    International Journal of Electronics, vol. 78, no. 2, pp. 327–332, 1995
  87. Multiphase sinusoidal oscillator using second-generation current conveyors
    International Journal of Electronics, vol. 78, no. 4, pp. 645–651, 1995
  88. CMOS four-quadrant multiplier using active attenuators
    International Journal of Electronics, vol. 79, no. 3, pp. 323–328, 1995
  89. Linear transformation all-pole filters based on current conveyors
    International Journal of Electronics, vol. 79, no. 4, pp. 439–445, 1995
  90. New current-feedback amplifier-based universal biquadratic filter
    IEEE Transactions on Instrumentation and Measurement, vol. 44, no. 4, pp. 915–917, 1995
  91. CMOS analog divider and four-quadrant multiplier using pool circuits
    IEEE Journal of Solid-State Circuits, vol. 30, no. 9, pp. 1025–1029, 1995
  92. Multiphase sinusoidal oscillator using the CFOA pole
    IEE Proceedings - Circuits, Devices and Systems, vol. 142, no. 1, p. 37, 1995
  93. Single-resistance-controlled/voltage-controlled oscillator using current conveyors and grounded capacitors
    Electronics Letters, vol. 31, no. 5, p. 337, 1995
  94. CMOS four-quadrant multiplier using triode transistors based on regulated cascode structure
    Electronics Letters, vol. 31, no. 12, p. 962, 1995
  95. High input impedance filters with low component spread using current-feedback amplifiers
    Electronics Letters, vol. 31, no. 13, p. 1042, 1995
  96. High-frequency linear transformation elliptic filters employing minimum number of OTAs
    Electronics Letters, vol. 31, no. 18, p. 1562, 1995
  97. Single-capacitor MOSFET-C integrator using OTRA
    Electronics Letters, vol. 31, no. 21, p. 1796, 1995
  98. Cascadable current-mode filters using single FTFN
    Electronics Letters, vol. 31, no. 23, p. 1965, 1995
  99. New multifunction filter using an inverting CCII and a voltage follower
    Electronics Letters, vol. 30, no. 7, p. 551, 1994
  100. CMOS four-quadrant multiplier using bias feedback techniques
    IEEE Journal of Solid-State Circuits, vol. 29, no. 6, pp. 750–752, 1994
  101. Dual-input differentiators and integrators with tunable time constants using current conveyors
    IEEE Transactions on Instrumentation and Measurement, vol. 43, no. 4, pp. 650–654, 1994
  102. New CCII-based current-mode biquadratic filters
    International Journal of Electronics, vol. 72, no. 2, pp. 243–252, 1992
  103. Euler differentiator with reduced channel length modulation
    Electronics Letters, vol. 28, no. 4, p. 419, 1992
  104. New CMOS NIC-based MOSFET-C filters
    Electronics Letters, vol. 27, no. 9, p. 772, 1991
  105. Current-mode oscillators using single current follower
    Electronics Letters, vol. 27, no. 22, p. 2056, 1991
  106. The single CCII biquads with high-input impedance
    IEEE Transactions on Circuits and Systems, vol. 38, no. 4, pp. 456–461, 1991
  107. New configurations for single CCII biquads
    International Journal of Electronics, vol. 70, no. 3, pp. 609–622, 1991
  108. Switched-current differentiator-based IIR and FIR filters
    International Journal of Electronics, vol. 71, no. 1, pp. 81–91, 1991
  109. TOCA-based electronically-tunable continuous-time filters
    International Journal of Electronics, vol. 71, no. 2, pp. 253–264, 1991
  110. New configuration for single-CCII first-order and biquadratic current-mode filters
    International Journal of Electronics, vol. 71, no. 4, pp. 637–644, 1991
  111. New CCII-based differentiator and its applications
    International Journal of Electronics, vol. 71, no. 4, pp. 645–652, 1991
  112. Electrically-programmable MOSFET-C filter
    International Journal of Electronics, vol. 68, no. 5, pp. 793–802, 1990
  113. MOSFET capacitor filters using unity gain CMOS current conveyors
    Electronics Letters, vol. 26, no. 18, p. 1430, 1990
  114. Cascadable current-mode single CCII biquads
    Electronics Letters, vol. 26, no. 24, p. 2005, 1990