Said Hamdioui received the M.S.E.E. and Ph.D. degrees (both with honors) from the Delft University of Technology (TUDelft), Delft, The Netherlands. He is currently coleading dependable nanocomputing research activities within the Computer Engineering Laboratory of TUDelft. Prior to joining TUDelft, Hamdioui spent more than 6 years within the industry; he worked for Intel Corporation, California, USA, for Philips Semiconductors R&D, France, and for NXP Semiconductors, The Netherlands. His research interests include dependable nanocomputing and VLSI Design and Test (i.e., defect/fault tolerance, reliability, hardware-security, design-for-testability, built-in-self-test, 3D stacked IC test, memory test, etc.). Hamdioui owns one patent and published one book and over 100 conference and journal papers; many of them are results of the cooperation with different industrial partners. He consulted for many companies (Intel, ST, Altera, Atmel, Renesas) in the area of embedded memory testing. He is strongly involved in the international test technology community. He delivered dozens of keynote speeches, distinguished lectures, and invited presentations and tutorial at major international forums/conferences and at leading semiconductor companies. Hamdioui is a Senior Member of the IEEE; he serves on the Editorial Board of the Journal of Electronic Testing: Theory and Applications. His honors include European Design Automation Association Outstanding Dissertation Award 2001, IEEE Nano and Nano Korea award at IEEE NANO 2010 Joint Symposium with NANO Korea 2010, Best Paper Award at International Conference on Design and Test of Integrated Systems in the nanoera 2011, and Intel Informal Award for developing test methods to improve outgoing Itanium processor quality. He is a leading Member of Cadence Academic Network on Dependability and Design-for-Testability, and he was nominated for The Young Academy of the Royal Netherlands Academy of Arts and Sciences in 2009.
Biography Updated on 1 January 2012