Xianlong Hong

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Articles in Scholarly Journals [Incomplete List]

  1. Application of optical proximity correction technology
    Science in China Series F: Information Sciences, vol. 51, no. 2, pp. 213–224, 2008
  2. Large scale P/G grid transient simulation using hierarchical relaxed approach
    Integration, the VLSI Journal, vol. 41, no. 1, pp. 153–160, 2008
  3. Zero skew clock routing in X-architecture based on an improved greedy matching algorithm☆
    Integration, the VLSI Journal, vol. 41, no. 3, pp. 426–438, 2008
  4. Thermal aware placement in 3D ICs using quadratic uniformity modeling approach
    Integration, the VLSI Journal, 2008
  5. Incremental Placement-Based Clock Network Minimization Methodology
    Tsinghua Science & Technology, vol. 13, no. 1, pp. 78–84, 2008
  6. IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 7, pp. 2064–2075, 2008
  7. Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp. 645–658, 2007
  8. Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp. 680–692, 2007
  9. Voltage Island Generation in Cell Based Dual-Vdd Design
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 1, pp. 267–273, 2007
  10. An efficient quadratic placement based on search space traversing technology
    Integration, the VLSI Journal, vol. 40, no. 3, pp. 253–260, 2007
  11. APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement?
    Integration, the VLSI Journal, vol. 40, no. 4, pp. 406–419, 2007
  12. Partitioning-based decoupling capacitor budgeting via sequence of linear programming?
    Integration, the VLSI Journal, vol. 40, no. 4, pp. 516–524, 2007
  13. FIDER: A Force-Balance-Based Interconnect Delay Driven Re-Synthesis Algorithm for Data-Path Optimization After Floorplan
    Tsinghua Science & Technology, vol. 12, no. 1, pp. 63–69, 2007
  14. A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design?
    Integration, the VLSI Journal, vol. 39, no. 4, pp. 457–473, 2006
  15. General Floorplans with L/T-Shaped Blocks Using Corner Block List
    Journal of Computer Science and Technology, vol. 21, no. 6, pp. 922–926, 2006
  16. Time-domain analysis methodology for large-scale RLC circuits and its applications
    Science in China Series F: Information Sciences, vol. 49, no. 5, pp. 665–680, 2006
  17. Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 12, pp. 2637–2646, 2006
  18. Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction Toward IP-Block-Based SOC Design
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 4, pp. 309–313, 2006
  19. VLSI Block Placement With Alignment Constraints
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 8, pp. 622–626, 2006
  20. Multilevel Routing With Redundant Via Insertion
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 10, pp. 1148–1152, 2006
  21. Power/Ground Network Optimization Considering Decap Leakage Currents
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 10, pp. 1012–1016, 2006
  22. A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 10, pp. 1007–1011, 2006
  23. Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2402–2412, 2006
  24. Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration
    ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 2, pp. 325–345, 2006
  25. Reliable buffered clock tree routing algorithm with process variation tolerance
    Science in China Series F, vol. 48, no. 5, p. 670, 2005
  26. Buffer Planning as an Integral Part of Floorplanning With Consideration of Routing Congestion
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp. 609–621, 2005
  27. Spanning Graph-Based Nonrectilinear Steiner Tree Algorithms
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 7, pp. 1066–1075, 2005
  28. Navigating Register Placement for Low Power Clock Network Design
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3405–3411, 2005
  29. Crosstalk and Congestion Driven Layer Assignment Algorithm
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 6, pp. 1565–1572, 2005
  30. A Fast Delay Computation for the Hybrid Structured Clock Network
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 7, pp. 1964–1970, 2005
  31. Preconditioned multi-zone boundary element analysis for fast 3D electric simulation
    Engineering Analysis with Boundary Elements, vol. 28, no. 9, pp. 1035–1044, 2004
  32. UTACO: A Unified Timing and Congestion Optimization Algorithm for Standard Cell Global Routing
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 3, pp. 358–365, 2004
  33. Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 7, pp. 1086–1094, 2004
  34. Stairway compaction using corner block list and its applications with rectilinear blocks
    ACM Transactions on Design Automation of Electronic Systems, vol. 9, no. 2, pp. 199–211, 2004
  35. Corner block list representation and its application with boundary constraints
    Science in China Series F, vol. 47, no. 1, p. 1, 2004
  36. A buffer planning algorithm for chip-level floorplanning
    Science in China Series F, vol. 47, no. 6, p. 763, 2004
  37. Corner Block List Representation and Its Application to Floorplan Optimization
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, no. 5, pp. 228–233, 2004
  38. An efficient hierarchical timing-driven Steiner tree algorithm for global routing
    Integration, the VLSI Journal, vol. 35, no. 2, pp. 69–84, 2003
  39. Increasing sensitivity to arsenic trioxide-induced apoptosis by altered telomere state
    European Journal of Pharmacology, vol. 474, no. 2-3, pp. 141–147, 2003
  40. The periodic solutions of discrete nagumo equation
    Journal of Shanghai University (English Edition), vol. 6, no. 2, pp. 97–100, 2002
  41. Differential cytostatic effect of sodium salicylate in human colorectal cancers using an individualized histoculture system
    Cancer Chemotherapy and Pharmacology, vol. 49, no. 6, pp. 473–478, 2002
  42. Floorplanning with abutment constraints based on corner block list
    Integration, the VLSI Journal, vol. 31, no. 1, pp. 65–77, 2001
  43. A macro cell array automatic layout system and its placement algorithm
    Computers in Industry, vol. 8, no. 2-3, pp. 255–263, 1987