João Antonio Martino

Joa~o Antonio Martino was born in Sao Paulo, Brazil. He has two nationalities: Brazilian and Italian. He received the Electrical Engineering degree from Faculdade de Engenharia Industrial (FEI) in 1981. He received the M.S. (NMOS Technology) and the Ph.D (CMOS Technology) degrees in 1984 and 1988, respectively, in electrical engineering (microelectronics) from University of Sao Paulo, Brazil. He worked as a postdoctoral researcher in joint collaboration between IMEC/KUL, Leuven, Belgium, and University of Sao Paulo, Brazil, from 1989 to 1994 in SOI Technology. He was a Full Professor and Head of the Electrical Engineering Department at FEI from 1996 to 2005. He was Head of Post-Graduate Program in Electrical Engineering at FEI from 2005 to 2006. Now he is a Full Professor at Electrical Engineering Department of University of Sao Paulo, Brazil. He is author and coauthor of more than 220 technical journal papers and conference presentation and author/editor of 4 books. He concludes the advisor work of 15 M.S. and 5 Ph.D. students. His expertise is in the area of the electrical characterization and modeling of SOI devices. He is also interested in SOI-CMOS fabrication process and Multiple Gate devices. He is Senior Member of IEEE, Member of Electrochemical Society, and the Chapter Chair of South Brazil Session of IEEE – Electron Device Society. He is Editor of Journal of Integrated Circuits and Systems of Brazilian Microelectronic Society.

Biography Updated on 23 February 2008

Articles in Scholarly Journals [Incomplete List]

  1. Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior
    Microelectronic Engineering, vol. 84, no. 9-10, pp. 2121–2124, 2007
  2. Study of the linear kink effect in PD SOI nMOSFETs
    Microelectronics Journal, vol. 38, no. 1, pp. 114–119, 2007
  3. The low-frequency noise behaviour of graded-channel SOI nMOSFETs
    Solid-State Electronics, vol. 51, no. 2, pp. 260–267, 2007
  4. Evaluation of triple-gate FinFETs with SiO2–HfO2–TiN gate stack under analog operation
    Solid-State Electronics, vol. 51, no. 2, pp. 285–291, 2007
  5. Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs
    Solid-State Electronics, vol. 51, no. 9, pp. 1194–1200, 2007
  6. Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs
    Solid-State Electronics, vol. 50, no. 1, pp. 52–57, 2006
  7. Investigation of back gate interface states by drain current hysteresis in PD-SOI n-MOSFETs
    Physica B: Condensed Matter, vol. 376-377, pp. 416–419, 2006
  8. Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications
    Microelectronics Journal, vol. 37, no. 2, pp. 137–144, 2006
  9. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
    Microelectronics Journal, vol. 37, no. 1, pp. 31–37, 2006
  10. Evaluation of graded-channel SOI MOSFET operation at high temperatures
    Microelectronics Journal, vol. 37, no. 7, pp. 601–607, 2006
  11. Impact of the twin-gate structure on the linear kink effect in PD SOI nMOSFETS
    Microelectronics Journal, vol. 37, no. 8, pp. 681–685, 2006
  12. The temperature mobility degradation influence on the zero temperature coefficient of partially and fully depleted SOI MOSFETs
    Microelectronics Journal, vol. 37, no. 9, pp. 952–957, 2006
  13. Modeling Silicon on Insulator MOS Transistors with Nonrectangular-Gate Layouts
    Journal of The Electrochemical Society, vol. 153, no. 3, p. G218, 2006
  14. Advantages of the Graded-Channel SOI FD MOSFET for Application as a Quasi-Linear Resistor
    IEEE Transactions on Electron Devices, vol. 52, no. 5, pp. 967–972, 2005
  15. Analysis of Temperature-Induced Saturation Threshold Voltage Degradation in Deep-Submicrometer Ultrathin SOI MOSFETs
    IEEE Transactions on Electron Devices, vol. 52, no. 10, pp. 2236–2242, 2005
  16. SOI technology characterization using SOI-MOS capacitor
    Solid-State Electronics, vol. 49, no. 1, pp. 109–116, 2005
  17. Impact of halo implantation on 0.13µm floating body partially depleted SOI n-MOSFETs in low temperature operation
    Solid-State Electronics, vol. 49, no. 8, pp. 1274–1281, 2005
  18. A simple current model for edgeless SOI nMOSFET and a 3-D analysis
    Solid-State Electronics, vol. 49, no. 8, pp. 1255–1261, 2005
  19. High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures
    Solid-State Electronics, vol. 49, no. 10, pp. 1569–1575, 2005
  20. Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices
    Solid-State Electronics, vol. 46, no. 9, pp. 1381–1387, 2002
  21. Physical and Electrical Characterization of Thin Nickel Films Obtained from Electroless Plating onto Aluminum
    physica status solidi (a), vol. 187, no. 1, pp. 75–84, 2001
  22. Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects
    Solid-State Electronics, vol. 44, no. 6, pp. 917–922, 2000
  23. Analog performance and application of graded-channel fully depleted SOI MOSFETs
    Solid-State Electronics, vol. 44, no. 7, pp. 1219–1222, 2000
  24. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs
    Solid-State Electronics, vol. 44, no. 11, pp. 1961–1969, 2000
  25. Extraction of the lightly doped drain concentration of fully depleted SOI NMOSFETs using the back gate bias effect
    Solid-State Electronics, vol. 44, no. 4, pp. 677–684, 2000
  26. Extraction of the oxide charges at the silicon substrate interface in Silicon-On-Insulator MOSFET's
    Solid-State Electronics, vol. 43, no. 11, pp. 2039–2046, 1999
  27. Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction
    Solid-State Electronics, vol. 43, no. 12, pp. 2191–2199, 1999
  28. Leakage Drain Current Behavior in an Accumulation Mode SOI p-Channel MOSFET Operating at High Temperatures
    Electrochemical and Solid-State Letters, vol. 2, no. 7, p. 345, 1999
  29. A Simple Method for Minimizing the Transient Effect in SOI nMOSFETs at Low Temperature
    Electrochemical and Solid-State Letters, vol. 2, no. 11, p. 585, 1999
  30. An Asymmetric Channel SOI nMOSFET for Reducing Parasitic Effects and Improving Output Characteristics
    Electrochemical and Solid-State Letters, vol. 3, no. 1, p. 50, 1999
  31. Influence of accumulation layer on interface trap density extraction
    Electronics Letters, vol. 34, no. 25, p. 2439, 1998
  32. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77 K
    Microelectronic Engineering, vol. 36, no. 1-4, pp. 375–378, 1997
  33. Substrate influences on fully depleted enhancement mode SOI MOSFETs at room temperature and at 77 K
    Solid-State Electronics, vol. 41, no. 1, pp. 111–119, 1997
  34. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature
    Solid-State Electronics, vol. 41, no. 9, pp. 1241–1246, 1997
  35. A new method for determining the front and back interface trap densities of accumulation mode SOI MOSFETs at 77K
    Solid-State Electronics, vol. 38, no. 10, pp. 1799–1803, 1995
  36. Transient effects in accumulation mode p-channel SOI MOSFET's operating at 77 K
    IEEE Transactions on Electron Devices, vol. 41, no. 4, pp. 519–523, 1994
  37. Simple method for the determination of the interface trap density at 77 K in fully depleted accumulation mode SOI MOSFETs
    Solid-State Electronics, vol. 36, no. 6, pp. 827–832, 1993
  38. Model for the potential drop in the silicon substrate for thin-film SOI MOSFETs
    Electronics Letters, vol. 26, no. 18, p. 1462, 1990