Denis Flandre

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http://www.nano.be/CVtoWEB/FlandreD_CV.pdf

Articles in Scholarly Journals [Incomplete List]

  1. The meta-stable dip (MSD) effect in SOI FinFETs
    Microelectronic Engineering, vol. 84, no. 4, pp. 590–593, 2007
  2. Harmonic distortion analysis using an improved charge sheet model for PD SOI MOSFETs
    Microelectronics Journal, vol. 38, no. 3, pp. 321–326, 2007
  3. The low-frequency noise behaviour of graded-channel SOI nMOSFETs
    Solid-State Electronics, vol. 51, no. 2, pp. 260–267, 2007
  4. Characterization of quantum efficiency, effective lifetime and mobility in thin film ungated SOI lateral PIN photodiodes
    Solid-State Electronics, vol. 51, no. 2, pp. 337–342, 2007
  5. Thin film fully-depleted SOI four-gate transistors
    Solid-State Electronics, vol. 51, no. 2, pp. 278–284, 2007
  6. Planar double-gate SOI MOS devices: Fabrication by wafer bonding over pre-patterned cavities and electrical characterization
    Solid-State Electronics, vol. 51, no. 2, pp. 231–238, 2007
  7. Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications
    Solid-State Electronics, vol. 51, no. 5, pp. 655–661, 2007
  8. Innovating SOI memory devices based on floating-body effects
    Solid-State Electronics, vol. 51, no. 10, pp. 1252–1262, 2007
  9. Specific features of multiple-gate MOSFET threshold voltage and subthreshold slope behavior at high temperatures
    Solid-State Electronics, vol. 51, no. 9, pp. 1185–1193, 2007
  10. Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity
    Solid-State Electronics, vol. 51, no. 9, pp. 1238–1244, 2007
  11. Characterization of FD SOI devices and VCO’s on thin dielectric membranes under pressure
    Solid-State Electronics, vol. 51, no. 9, pp. 1229–1237, 2007
  12. Dynamic differential self-timed logic families for robust and low-power security ICs
    Integration, the VLSI Journal, vol. 40, no. 3, pp. 355–364, 2007
  13. Electrical detection of DNA hybridization: Three extraction techniques based on interdigitated Al/Al2O3 capacitors
    Biosensors and Bioelectronics, vol. 22, no. 9-10, pp. 2199–2207, 2007
  14. Bulk and surface micromachined MEMS in thin film SOI technology
    Electrochimica Acta, vol. 52, no. 8, pp. 2850–2861, 2007
  15. Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode
    IEEE Journal of Solid-State Circuits, vol. 42, no. 3, pp. 689–702, 2007
  16. Frequency Variation of the Small-Signal Output Conductance of Decananometer MOSFETs Due to Substrate Crosstalk
    IEEE Electron Device Letters, vol. 28, no. 5, pp. 419–421, 2007
  17. On the Origin of the Excess Low-Frequency Noise in Graded-Channel Silicon-on-Insulator nMOSFETs
    IEEE Electron Device Letters, vol. 28, no. 10, pp. 919–921, 2007
  18. Abnormal Drain Current (ADC) Effect and Its Mechanism in FD SOI MOSFETs
    IEEE Electron Device Letters, vol. 27, no. 2, pp. 123–126, 2006
  19. C8-continuous high-temperature model for low-doped accumulation mode silicon-on-insulator pMOSFETs
    Solid-State Electronics, vol. 50, no. 7-8, pp. 1261–1268, 2006
  20. Monolithically integrated 10 Gbit/s photodiode and transimpedance amplifier in thin-film SOI CMOS technology
    Electronics Letters, vol. 42, no. 24, p. 1420, 2006
  21. Self-cascode SOI versus graded-channel SOI MOS transistors
    IEE Proceedings - Circuits, Devices and Systems, vol. 153, no. 5, p. 461, 2006
  22. Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications
    Microelectronics Journal, vol. 37, no. 2, pp. 137–144, 2006
  23. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
    Microelectronics Journal, vol. 37, no. 1, pp. 31–37, 2006
  24. Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks
    Microelectronics Journal, vol. 37, no. 9, pp. 997–1006, 2006
  25. Characterization and Design Methodology for Low-Distortion MOSFET-C Analog Structures in Multithreshold Deep-Submicrometer SOI CMOS Technologies
    IEEE Transactions on Electron Devices, vol. 53, no. 2, pp. 263–269, 2006
  26. Analog/RF Performance of Multiple Gate SOI Devices: Wideband Simulations and Characterization
    IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1088–1095, 2006
  27. Fluctuation and Noise Letters [An Interdisciplinary Scientific Journal on Random Processes in Physical, Biological and Technological Systems], vol. 6, no. 1, p. L29, 2006
  28. Advantages of the Graded-Channel SOI FD MOSFET for Application as a Quasi-Linear Resistor
    IEEE Transactions on Electron Devices, vol. 52, no. 5, pp. 967–972, 2005
  29. Physical Modeling and Design of Thin-Film SOI Lateral PIN Photodiodes
    IEEE Transactions on Electron Devices, vol. 52, no. 6, pp. 1116–1122, 2005
  30. SOI-CMOS compatible low-power gas sensor using sputtered and drop-coated metal-oxide active layers
    Microsystem Technologies, vol. 12, no. 1-2, pp. 160–168, 2005
  31. On the great potential of non-doped MOSFETs for analog applications in partially-depleted SOI CMOS process
    Solid-State Electronics, vol. 49, no. 5, pp. 708–715, 2005
  32. A new multi-valued current-mode adder based on negative-differential resistance using ULP diodes
    Solid-State Electronics, vol. 49, no. 7, pp. 1185–1191, 2005
  33. FinFET analogue characterization from DC to 110GHz
    Solid-State Electronics, vol. 49, no. 9, pp. 1488–1496, 2005
  34. A new memory effect (MSD) in fully depleted SOI MOSFETs
    Solid-State Electronics, vol. 49, no. 9, pp. 1547–1555, 2005
  35. A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation
    Solid-State Electronics, vol. 49, no. 10, pp. 1683–1692, 2005
  36. High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures
    Solid-State Electronics, vol. 49, no. 10, pp. 1569–1575, 2005
  37. Comparison of DNA detection methods using nanoparticles and silver enhancement
    IEE Proceedings - Nanobiotechnology, vol. 152, no. 1, p. 3, 2005
  38. A revised reverse gated-diode technique for determining generation parameters in thin-film silicon-on-insulator devices and its application at high temperatures
    Journal of Applied Physics, vol. 97, no. 9, p. 093718, 2005
  39. Analysis of quasi double gate method for performance prediction of deep submicron double gate SOI MOSFETs
    Semiconductor Science and Technology, vol. 20, no. 5, pp. 423–429, 2005
  40. High frequency degradation of body-contacted PD SOI MOSFET output conductance
    Semiconductor Science and Technology, vol. 20, no. 5, pp. 469–472, 2005
  41. Effective mobility in FinFET structures with HfO and SiON gate dielectrics and TaN gate electrode
    Microelectronic Engineering, vol. 80, pp. 386–389, 2005
  42. Accurate Effective Mobility Extraction by Split C–V Technique in SOI MOSFETs: Suppression of the Influence of Floating-Body Effects
    IEEE Electron Device Letters, vol. 26, no. 10, pp. 749–751, 2005
  43. SOI CMOS Compatible Low-Power Microheater Optimization for the Fabrication of Smart Gas Sensors
    IEEE Sensors Journal, vol. 4, no. 5, pp. 670–680, 2004
  44. AC Behavior of Gate-Induced Floating Body Effects in Ultrathin Oxide PD SOI MOSFETs
    IEEE Electron Device Letters, vol. 25, no. 2, pp. 104–106, 2004
  45. Thin films stress extraction using micromachined structures and wafer curvature measurements
    Microelectronic Engineering, vol. 76, no. 1-4, pp. 219–226, 2004
  46. Sensitive DNA electrical detection based on interdigitated Al/Al2O3 microelectrodes
    Sensors and Actuators B: Chemical, vol. 98, no. 2-3, pp. 269–274, 2004
  47. Determination of film and surface recombination in thin-film SOI devices using gated-diode technique
    Solid-State Electronics, vol. 48, no. 3, pp. 389–399, 2004
  48. Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications
    Solid-State Electronics, vol. 48, no. 6, pp. 947–959, 2004
  49. Composite ULP diode fabrication, modelling and applications in multi-Vth FD SOI CMOS technology
    Solid-State Electronics, vol. 48, no. 6, pp. 1017–1025, 2004
  50. Integral function method for determination of nonlinear harmonic distortion
    Solid-State Electronics, vol. 48, no. 12, pp. 2225–2234, 2004
  51. LDMOS in SOI technology with very-thin silicon film
    Solid-State Electronics, vol. 48, no. 12, pp. 2263–2270, 2004
  52. Fluctuation and Noise Letters [An Interdisciplinary Scientific Journal on Random Processes in Physical, Biological and Technological Systems], vol. 4, no. 2, p. L345, 2004
  53. Power-Delay Product Minimization in High-Performance 64-bit Carry-Select Adders
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 3, pp. 235–244, 2004
  54. FD MOS SOI circuit to enhance the ratio of illuminated to dark current of a co-integrated a-Si:H photodiode
    Microelectronics Reliability, vol. 43, no. 2, pp. 189–193, 2003
  55. A review of leakage current in SOI CMOS ICs: impact on parametric testing techniques
    Solid-State Electronics, vol. 47, no. 11, pp. 1959–1967, 2003
  56. Immobilization of DNA on CMOS compatible materials
    Sensors and Actuators B: Chemical, vol. 92, no. 1-2, pp. 90–97, 2003
  57. Floating effective back-gate effect on the small-signal output conductance of soi mosfets
    IEEE Electron Device Letters, vol. 24, no. 6, pp. 414–416, 2003
  58. Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications
    IEEE Transactions on Electron Devices, vol. 50, no. 1, pp. 106–110, 2003
  59. Influence of device engineering on the analog and RF performances of SOI MOSFETs
    IEEE Transactions on Electron Devices, vol. 50, no. 3, pp. 577–588, 2003
  60. SOI technology for future high-performance smart cards
    IEEE Micro, vol. 23, no. 3, pp. 58–67, 2003
  61. SOI n-MOSFET low-frequency noise measurements and modeling from room temperature up to 250°C
    IEEE Transactions on Electron Devices, vol. 49, no. 7, pp. 1289–1295, 2002
  62. On the high-temperature subthreshold slope of thin-film SOI MOSFETs
    IEEE Electron Device Letters, vol. 23, no. 3, pp. 148–150, 2002
  63. 25 to 300°C ultra-low-power voltage reference compatible with standard SOI CMOS process
    Electronics Letters, vol. 38, no. 19, p. 1103, 2002
  64. A method to extract mobility degradation and total series resistance of fully-depleted SOI MOSFETs
    IEEE Transactions on Electron Devices, vol. 49, no. 1, pp. 82–88, 2002
  65. 0.25 µm fully depleted SOI MOSFETs for RF mixed analog-digital circuits, including a comparison with partially depleted devices with relation to high frequency noise parameters
    Solid-State Electronics, vol. 46, no. 3, pp. 379–386, 2002
  66. New method for determination of harmonic distortion in SOI FD transistors
    Solid-State Electronics, vol. 46, no. 1, pp. 103–108, 2002
  67. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs
    Solid-State Electronics, vol. 46, no. 8, pp. 1215–1225, 2002
  68. Analysis of the thin-film SOI lateral bipolar transistor and optimization of its output characteristics for high-temperature applications
    Solid-State Electronics, vol. 46, no. 9, pp. 1339–1343, 2002
  69. A modified Bosch-type process for precise surface micromachining of polysilicon
    Journal of Micromechanics and Microengineering, vol. 12, no. 3, pp. 328–333, 2002
  70. Investigation of Deep Submicron Single and Double Gate SOI MOSFETs in Accumulation Mode for Enhanced Performance
    Electrochemical and Solid-State Letters, vol. 4, no. 3, p. G28, 2001
  71. Hall effect measurements in double-gate SOI MOSFETs
    Solid-State Electronics, vol. 45, no. 10, pp. 1793–1798, 2001
  72. Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems
    Solid-State Electronics, vol. 45, no. 4, pp. 541–549, 2001
  73. Deep-submicrometer DC-to-RF SOI MOSFET macro-model
    IEEE Transactions on Electron Devices, vol. 48, no. 9, pp. 1981–1988, 2001
  74. Integrated sensor and electronic circuits in fully depleted SOI technology for high-temperature applications
    IEEE Transactions on Industrial Electronics, vol. 48, no. 2, pp. 272–280, 2001
  75. Process alternative: SOI for heterogeneous systems
    Microelectronic Engineering, vol. 54, no. 1-2, pp. 49–62, 2000
  76. New experiments on the electrodeposition of iron in porous silicon
    Microelectronics Reliability, vol. 40, no. 4-5, pp. 877–879, 2000
  77. Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects
    Solid-State Electronics, vol. 44, no. 6, pp. 917–922, 2000
  78. Analog performance and application of graded-channel fully depleted SOI MOSFETs
    Solid-State Electronics, vol. 44, no. 7, pp. 1219–1222, 2000
  79. Analog Integrated Circuits and Signal Processing, vol. 21, no. 3, pp. 213–228, 1999
  80. Carrier lifetime extraction in fully depleted dual-gate SOI devices
    IEEE Electron Device Letters, vol. 20, no. 5, pp. 209–211, 1999
  81. Gate-all-around OTA's for rad-hard and high-temperature analog applications
    IEEE Transactions on Nuclear Science, vol. 46, no. 4, pp. 1242–1249, 1999
  82. A physically-based C/sub 8/-continuous model for accumulation-mode SOI pMOSFETs
    IEEE Transactions on Electron Devices, vol. 46, no. 12, pp. 2295–2303, 1999
  83. High-temperature sigma-delta modulator in thin-film fully-depleted SOI technology
    Electronics Letters, vol. 35, no. 9, p. 749, 1999
  84. An Asymmetric Channel SOI nMOSFET for Reducing Parasitic Effects and Improving Output Characteristics
    Electrochemical and Solid-State Letters, vol. 3, no. 1, p. 50, 1999
  85. Potential and modeling of 1-µm SOI CMOS operational transconductance amplifiers for applications up to 1 GHz
    IEEE Journal of Solid-State Circuits, vol. 33, no. 4, pp. 640–643, 1998
  86. Magnetic-field sensor based on a thin-film SOI transistor
    Sensors and Actuators A: Physical, vol. 67, no. 1-3, pp. 96–101, 1998
  87. Fully depleted SOI-CMOS technology for high temperature IC applications
    Materials Science and Engineering B, vol. 46, no. 1-3, pp. 1–7, 1997
  88. Potential and modelling of 1 [micro sign]m 1 GHz SOI CMOS OTAs
    Electronics Letters, vol. 33, no. 9, p. 774, 1997
  89. Unified 1/f noise SOI MOSFET modelling for circuit simulation
    Electronics Letters, vol. 33, no. 21, p. 1781, 1997
  90. Comparison of self-heating effect in GAA and SOI mosfets
    Microelectronics and Reliability, vol. 37, no. 1, pp. 61–75, 1997
  91. Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology
    IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1006–1012, 1997
  92. Substrate crosstalk reduction using SOI technology
    IEEE Transactions on Electron Devices, vol. 44, no. 12, pp. 2252–2261, 1997
  93. Comparison of TiSi[sub 2],?CoSi[sub 2], and NiSi for Thin-Film Silicon-on-Insulator Applications
    Journal of The Electrochemical Society, vol. 144, no. 7, p. 2437, 1997
  94. A physically-based C/sub 8/-continuous fully-depleted SOI MOSFET model for analog applications
    IEEE Transactions on Electron Devices, vol. 43, no. 4, pp. 568–575, 1996
  95. Design of SOI CMOS operational amplifiers for applications up to 300°C
    IEEE Journal of Solid-State Circuits, vol. 31, no. 2, pp. 179–186, 1996
  96. A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA
    IEEE Journal of Solid-State Circuits, vol. 31, no. 9, pp. 1314–1319, 1996
  97. The effect of series resistance on threshold voltage measurement techniques for fully depleted SOI MOSFETs
    Solid-State Electronics, vol. 39, no. 1, pp. 89–94, 1996
  98. Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits
    Solid-State Electronics, vol. 39, no. 4, pp. 455–460, 1996
  99. Measurement and modeling of thin-film accumulation-mode SOI p-MOSFET intrinsic gate capacitances
    Solid-State Electronics, vol. 39, no. 7, pp. 1071–1078, 1996
  100. Measurement and two-dimensional simulation of thin-film SOI MOSFETs: Intrinsic gate capacitances at elevated temperatures
    Solid-State Electronics, vol. 39, no. 11, pp. 1613–1619, 1996
  101. Improvement of SOI MOS current-mirror performances using serial-parallel association of transistors
    Electronics Letters, vol. 32, no. 4, p. 278, 1996
  102. Charge-sheet modelling of MOS I-V fundamental nonlinearities in MOSFET-C continuous-time filters
    Electronics Letters, vol. 31, no. 17, p. 1419, 1995
  103. Moderate inversion model of ultrathin double-gate nMOS/SOI transistors
    Solid-State Electronics, vol. 38, no. 1, pp. 171–176, 1995
  104. Silicon-on-insulator technology for high temperature metal oxide semiconductor devices and circuits
    Materials Science and Engineering B, vol. 29, no. 1-3, pp. 7–12, 1995
  105. Theoretical considerations for SRAM total-dose hardening
    IEEE Transactions on Nuclear Science, vol. 42, no. 2, pp. 83–91, 1995
  106. Modeling of ultrathin double-gate nMOS/SOI transistors
    IEEE Transactions on Electron Devices, vol. 41, no. 5, pp. 715–720, 1994
  107. Radiation-hard design for SOI MOS inverters
    IEEE Transactions on Nuclear Science, vol. 41, no. 2, pp. 402–407, 1994
  108. Latch and hot-electron gate current in accumulation-mode SOI p-MOSFET's
    IEEE Electron Device Letters, vol. 15, no. 5, pp. 157–159, 1994
  109. Subthreshold slope of long-channel, accumulation-mode p-channel SOI MOSFETs
    Solid-State Electronics, vol. 37, no. 2, pp. 289–294, 1994
  110. Comments on “numerical analysis of small-signal characteristics of a fully depleted SOI MOSFET”
    Solid-State Electronics, vol. 37, no. 7, pp. 1447–1448, 1994
  111. Kink-like effect in long n-channel twin-gate fully-depleted SOI MOSFETs
    Electronics Letters, vol. 30, no. 17, p. 1456, 1994
  112. P+-P-P+ pseudo-bipolar lateral SOI transistor
    Electronics Letters, vol. 30, no. 18, p. 1543, 1994
  113. Comparison of SOI versus bulk performances of CMOS micropower single-stage OTAs
    Electronics Letters, vol. 30, no. 23, p. 1933, 1994
  114. Extraction of physical device dimensions of SOI MOSFETs from gate capacitance measurements
    Electronics Letters, vol. 29, no. 7, p. 586, 1993
  115. Evidence of different conduction mechanisms in accumulation-mode p-channel SOI MOSFET's at room and liquid-helium temperatures
    IEEE Transactions on Electron Devices, vol. 40, no. 4, pp. 727–732, 1993
  116. Analysis of floating substrate effects on the intrinsic gate capacitance of SOI MOSFETSs using two-dimensional device simulation
    IEEE Transactions on Electron Devices, vol. 40, no. 10, pp. 1789–1796, 1993
  117. Demonstration of the potential of accumulation-mode MOS transistors on SOI substrates for high-temperature operation (150-300 degrees C)
    IEEE Electron Device Letters, vol. 14, no. 1, pp. 10–12, 1993
  118. Measurement and simulation of floating substrate effects on the intrinsic gate capacitance characteristics of SOI n-MOSFETs
    Electronics Letters, vol. 28, no. 10, p. 967, 1992
  119. Physics and performances of accumulation-mode SOI p-MOSFET's from low (77 K) to high (150–320°C) temperatures
    Microelectronic Engineering, vol. 19, no. 1-4, pp. 803–806, 1992
  120. Characteristics of nMOS/GAA (Gate-All-Around) transistors near threshold
    Microelectronic Engineering, vol. 19, no. 1-4, pp. 815–818, 1992
  121. Extended theoretical analysis of the steady-state linear behaviour of accumulation-mode, long-channel p-MOSFETs on SOI substrates
    Solid-State Electronics, vol. 35, no. 8, pp. 1085–1092, 1992
  122. Interpretation of quasi-static C-V characteristics of MOSOS capacitors on SOI substrates
    Electronics Letters, vol. 27, no. 1, p. 43, 1991
  123. Problems in designing thin-film accumulation-mode p-channel SOI MOSFETs for CMOS digital circuit environment
    Electronics Letters, vol. 27, no. 14, p. 1280, 1991