Marcelo Antonio Pavanello

Marcelo Antonio Pavanello was born in Santo André, Brazil, in 1970. He received the Electrical Engineering degree from Faculdade de Engenharia Industrial (FEI) in 1993, the M.S. and Ph.D. degrees in 1996 and 2000, respectively, in microelectronics from University of São Paulo, Brazil. From August to December 1998, he was with Laboratoire de Microélectronique from Université Catholique de Louvain (UCL), Belgium, working in the fabrication and electrical characterization of novel Silicon-On-Insulator (SOI) transistors. From 2000 to 2002, he was with the Center of Semiconductor Components, State University of Campinas, Brazil, where he worked as a Postdoctoral Researcher in the development of an CMOS n-well process. Since 2003, he joined Centro Universitario da FEI, where he is now a Professor at Electrical Engineering Department of FEI and Head of Post-Graduate Program in Electrical Engineering. Since 2007 he serves as IEEE EDS Distinguished Lecturer. His current interests are the fabrication, electrical characterization, simulation, and modeling of advanced multiple-gate SOI CMOS transistors, and design of analog cells using novel SOI devices. Dr. Pavanello is a Senior Member of the IEEE, Member of The Electrochemical Society and Brazilian Microelectronics Society. He is also a Research Associate to the National Council for Scientific Development (CNPq), Brazil.

Biography Updated on 20 February 2008

Personal Home Page

http://buscatextual.cnpq.br/buscatextual/visualizacv.jsp?id=K4797574Z6

Articles in Scholarly Journals [Incomplete List]

  1. Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior
    Microelectronic Engineering, vol. 84, no. 9-10, pp. 2121–2124, 2007
  2. The low-frequency noise behaviour of graded-channel SOI nMOSFETs
    Solid-State Electronics, vol. 51, no. 2, pp. 260–267, 2007
  3. Evaluation of triple-gate FinFETs with SiO2–HfO2–TiN gate stack under analog operation
    Solid-State Electronics, vol. 51, no. 2, pp. 285–291, 2007
  4. Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs
    Solid-State Electronics, vol. 51, no. 9, pp. 1194–1200, 2007
  5. Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications
    Microelectronics Journal, vol. 37, no. 2, pp. 137–144, 2006
  6. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
    Microelectronics Journal, vol. 37, no. 1, pp. 31–37, 2006
  7. Evaluation of graded-channel SOI MOSFET operation at high temperatures
    Microelectronics Journal, vol. 37, no. 7, pp. 601–607, 2006
  8. Advantages of the Graded-Channel SOI FD MOSFET for Application as a Quasi-Linear Resistor
    IEEE Transactions on Electron Devices, vol. 52, no. 5, pp. 967–972, 2005
  9. Analysis of Temperature-Induced Saturation Threshold Voltage Degradation in Deep-Submicrometer Ultrathin SOI MOSFETs
    IEEE Transactions on Electron Devices, vol. 52, no. 10, pp. 2236–2242, 2005
  10. Impact of halo implantation on 0.13µm floating body partially depleted SOI n-MOSFETs in low temperature operation
    Solid-State Electronics, vol. 49, no. 8, pp. 1274–1281, 2005
  11. A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation
    Solid-State Electronics, vol. 49, no. 10, pp. 1683–1692, 2005
  12. High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures
    Solid-State Electronics, vol. 49, no. 10, pp. 1569–1575, 2005
  13. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs
    Solid-State Electronics, vol. 46, no. 8, pp. 1215–1225, 2002
  14. Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects
    Solid-State Electronics, vol. 44, no. 6, pp. 917–922, 2000
  15. Analog performance and application of graded-channel fully depleted SOI MOSFETs
    Solid-State Electronics, vol. 44, no. 7, pp. 1219–1222, 2000
  16. Extraction of the oxide charges at the silicon substrate interface in Silicon-On-Insulator MOSFET's
    Solid-State Electronics, vol. 43, no. 11, pp. 2039–2046, 1999
  17. An Asymmetric Channel SOI nMOSFET for Reducing Parasitic Effects and Improving Output Characteristics
    Electrochemical and Solid-State Letters, vol. 3, no. 1, p. 50, 1999
  18. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77 K
    Microelectronic Engineering, vol. 36, no. 1-4, pp. 375–378, 1997
  19. Substrate influences on fully depleted enhancement mode SOI MOSFETs at room temperature and at 77 K
    Solid-State Electronics, vol. 41, no. 1, pp. 111–119, 1997
  20. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature
    Solid-State Electronics, vol. 41, no. 9, pp. 1241–1246, 1997