Yong-Bin Kim

Yong-Bin Kim was born in Seoul, South Korea, in 1960. He received the B.S. degree in electrical engineering from Sogang University in Seoul, South Korea, in 1982, the M.S. and Ph.D. degrees both in electrical and computer engineering from New Jersey Institute of Technology and Colorado State University, in 1989 and 1996, respectively. From 1982 to 1987, Dr. Kim was with Electronics and Telecommunications Research Institute(ETRI) in Daejon, South Korea as a Member of Technical Staff, and was involved in telecommunication chip designs. From 1990 to 1993, he was with Intel Corp. as a Senior Design Engineer, and was involved in microcontroller chip design and Intel Pentium Pro microprocessor chip design. From 1993 to 1996, he was with Hewlett Packard Co., Fort Collins, Colo, USA, as a Member of Technical Staff, and was involved in HP PA-8000 RISC microprocessor chip design. From 1996 to 1998, he was with Sun Microsystems, Palo Alto, Calif, USA, as an Individual Technical Contributor, and was involved in 1.5 GHz Ultra Sparc5 CPU chip design. From 1998 to 2000, he was an Assistant Professor in the Department of Electrical Engineering of University of Utah. He is currently an Associate Professor in the Department of Electrical and Computer Engineering at Northeastern University. His research focuses on high-speed low-power digital and analog VLSI circuit design, Physical CAD, and system-on-chip design methodology.

Biography Updated on 18 November 2007

Personal Home Page

http://www.ece.neu.edu/faculty/ybk

Articles in Scholarly Journals [Incomplete List]

  1. Monomer Control for Error Tolerance in DNA Self-Assembly
    Journal of Electronic Testing, 2008
  2. Measuring the Timing Jitter of ATE in the Frequency Domain
    IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 1, pp. 280–289, 2006
  3. Evaluating the Yield of Repairable SRAMs for ATE
    IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 5, pp. 1704–1712, 2006
  4. A High-Efficiency Fully Digital Synchronous Buck Converter Power Delivery System Based on a Finite-State Machine
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 3, pp. 229–240, 2006
  5. ASLIC: A low power CMOS analog circuit design automation
    Integration, the VLSI Journal, vol. 39, no. 3, pp. 157–181, 2006
  6. Design metal-dot based QCA circuits using SPICE model
    Microelectronics Journal, vol. 37, no. 8, pp. 821–827, 2006
  7. SET-based nano-circuit simulation and design method using HSPICE
    Microelectronics Journal, vol. 36, no. 8, pp. 741–748, 2005
  8. Environmental-Based Characterization of SoC-Based Instrumentation Systems for Stratified Testing
    IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 3, pp. 1241–1248, 2005
  9. A CMOS Subbandgap Reference Circuit With 1-V Power Supply Voltage
    IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 252–255, 2004
  10. Balanced dual-stage repair for dependable embedded memory cores
    Journal of Systems Architecture, vol. 50, no. 5, pp. 281–285, 2004
  11. Fast and accurate DAC modeling techniques based on wavelet theory
    Microelectronics Journal, vol. 35, no. 5, pp. 451–460, 2004
  12. Guest editors' introduction: clockless VLSI systems
    IEEE Design & Test of Computers, vol. 20, no. 6, pp. 5–8, 2003
  13. Automating wave-pipelined circuit design
    IEEE Design & Test of Computers, vol. 20, no. 6, pp. 51–58, 2003
  14. Analysis and measurement of timing jitter induced by radiated emi noise in automatic test equipment
    IEEE Transactions on Instrumentation and Measurement, vol. 52, no. 6, pp. 1749–1755, 2003