Niraj K. Jha

Niraj K. Jha received his B.Tech. degree in electronics and electrical communication engineering from IIT, Kharagpur, India, in 1981, M.S. degree in electrical engineering from SUNY at Stony Brook, NY, in 1982, and Ph.D. degree in electrical engineering from University of Illinois at Urbana-Champaign, Ill, in 1985. He is a Professor of Electrical Engineering at Princeton University. He is a Fellow of IEEE and ACM. He is currently serving as the Editor-in-Chief of IEEE Transactions on VLSI Systems, and an Associate Editor of IEEE Transactions on Circuits and Systems II: Express Briefs, IEEE Transactions on Computer-Aided Design, and Journal of Low Power Electronics. He has served as an Editor of Journal of Electronic Testing: Theory and Applications (JETTA). He has also served as the Program Chairman of the 1992 Workshop on Fault-Tolerant Parallel and Distributed Systems and the 2004 International Conference on Embedded and Ubiquitous Computing (he gave the keynote speech on nanotechnology at this conference in 2005). He served as the Director of the Center for Embedded System-on-chip Design funded by New Jersey Commission on Science and Technology. He is the recipient of the AT&T Foundation Award and NEC Preceptorship Award for research excellence, NCR Award for teaching excellence, and Princeton University Graduate Mentoring Award. He has coauthored three books on digital system testing and power optimization. He has authored or coauthored more than 310 papers, seven of which have won the Best Paper Award. A paper of his was selected for The Best of ICCAD and another for IEEE Micro Magazine’s Top Picks of Computer Architecture Conferences. He has received 12 US patents. His research interests include nanotechnology, power/thermal efficient hardware and software design, computer-aided design of integrated circuits and systems, secure computing, and digital system testing.

Biography Updated on 10 October 2007

Personal Home Page

http://www.ee.princeton.edu/people/Jha.php

Articles in Scholarly Journals [Incomplete List]

  1. SLOPES: Hardware–Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3, pp. 508–526, 2007
  2. Automated Energy/Performance Macromodeling of Embedded Software
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3, pp. 542–552, 2007
  3. Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 6, pp. 1161–1170, 2007
  4. Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 7, pp. 1233–1245, 2007
  5. Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 7, pp. 1339–1345, 2007
  6. A Test Generation Framework for Quantum Cellular Automata Circuits
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 1, pp. 24–36, 2007
  7. Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 3, pp. 296–308, 2007
  8. Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 4, pp. 427–437, 2007
  9. Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 4, pp. 465–470, 2007
  10. Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 5, pp. 518–530, 2007
  11. Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 5, pp. 605–609, 2007
  12. Architectural Support for Run-Time Validation of Program Data Properties
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 5, pp. 546–559, 2007
  13. Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 6, pp. 699–710, 2007
  14. Energy-Efficient Graphical User Interface Design
    IEEE Transactions on Mobile Computing, vol. 5, no. 7, pp. 846–859, 2006
  15. A Scalable Synthesis Methodology for Application-Specific Processors
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 11, pp. 1175–1188, 2006
  16. Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 12, pp. 1295–1308, 2006
  17. Application-Specific Heterogeneous Multiprocessor Synthesis Using Extensible Processors
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 9, pp. 1589–1602, 2006
  18. RTL-Aware Cycle-Accurate Functional Power Estimation
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 2103–2117, 2006
  19. Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 2193–2206, 2006
  20. Use of Computation-Unit Integrated Memories in High-Level Synthesis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 1969–1989, 2006
  21. An Algorithm for Synthesis of Reversible Logic Circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2317–2330, 2006
  22. Temperature-Aware On-Chip Networks
    IEEE Micro, vol. 26, no. 1, pp. 130–139, 2006
  23. Threshold Network Synthesis and Optimization and Its Application to Nanotechnologies
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, pp. 107–118, 2005
  24. Interconnect-Aware Low-Power High-Level Synthesis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 336–351, 2005
  25. Joint Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-Time Embedded Systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 7, pp. 1030–1041, 2005
  26. Generation of Distributed Logic-Memory Architectures Through High-Level Synthesis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 11, pp. 1694–1711, 2005
  27. Low-power system scheduling, synthesis and displays
    IEE Proceedings - Computers and Digital Techniques, vol. 152, no. 3, p. 344, 2005
  28. Memory Binding for Performance Optimization of Control-Flow Intensive Behavioral Descriptions
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 5, pp. 513–524, 2005
  29. An Algorithm for Nanopipelining of RTD-Based Circuits and Architectures
    IEEE Transactions On Nanotechnology, vol. 4, no. 2, pp. 159–167, 2005
  30. Input Space Adaptive Design: A High-Level Methodology for Optimizing Energy and Performance
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 6, pp. 590–602, 2004
  31. DESP: a distributed economics-based subcontracting protocol for computation distribution in power-aware mobile ad hoc networks
    IEEE Transactions on Mobile Computing, vol. 3, no. 1, pp. 33–45, 2004
  32. Corrigendum to “Combined effects of food quantity and quality on Cd, Cr, and Zn assimilation to the green mussel, Perna viridis ”[J. Exp. Mar. Biol. Ecol. 290 (2003) 49–69]
    Journal of Experimental Marine Biology and Ecology, vol. 299, no. 2, p. 267, 2004
  33. COWLS: Hardware–Software Cosynthesis of Wireless Low-Power Distributed EmbeddedClient–Server Systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 1, pp. 2–16, 2004
  34. Common-Case Computation: A High-Level Energy and Performance Optimization Technique
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 1, pp. 33–49, 2004
  35. Custom-Instruction Synthesis for Extensible-Processor Platforms
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 2, pp. 216–228, 2004
  36. A Hybrid Energy-Estimation Technique for Extensible Processors
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 5, pp. 652–664, 2004
  37. Resource Budgeting for Multiprocess High-Level Synthesis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 7, pp. 1010–1019, 2004
  38. Register Binding-Based RTL Power Management for Control-Flow Intensive Designs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 8, pp. 1175–1183, 2004
  39. High-level macro-modeling and estimation techniques for switching activity and power consumption
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 4, pp. 538–557, 2003
  40. Analysis of power dissipation in embedded systems using real-time operating systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 5, pp. 615–627, 2003
  41. A simulation framework for energy-consumption analysis of OS-driven embedded applications
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 9, pp. 1284–1294, 2003
  42. BMC Psychiatry, vol. 3, no. 1, p. 11, 2003
  43. Leakage power analysis and reduction during behavioral synthesis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 6, pp. 876–885, 2002
  44. High-level test compaction techniques
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 827–841, 2002
  45. High-level energy macromodeling of embedded software
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 9, pp. 1037–1050, 2002
  46. Test synthesis of systems-on-a-chip
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 10, pp. 1211–1217, 2002
  47. TAO: regular expression-based register-transfer level testability analysis and optimization
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 6, pp. 824–832, 2001
  48. Clock selection for performance optimization of control-flow intensive behaviors
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, pp. 158–165, 2001
  49. Testing of core-based systems-on-a-chip
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 3, pp. 426–439, 2001
  50. Fault-diagnosis-based technique for establishing RTL and gate-level correspondences
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 12, pp. 1414–1425, 2001
  51. A BIST scheme for RTL circuits based on symbolic testability analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 1, pp. 111–128, 2000
  52. Incorporating speculative execution into scheduling of control-flow-intensive designs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 3, pp. 308–324, 2000
  53. A fast and low-cost testing technique for core-based system-chips
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 8, pp. 863–877, 2000
  54. TAO-BIST: A framework for testability analysis and optimization for built-in self-test of RTL circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 8, pp. 894–906, 2000
  55. Behavioral synthesis of fault secure controller/datapaths based on aliasing probability analysis
    IEEE Transactions on Computers, vol. 49, no. 9, pp. 865–885, 2000
  56. COFTA: hardware-software co-synthesis of heterogeneous distributed embedded systems for low overhead fault tolerance
    IEEE Transactions on Computers, vol. 48, no. 4, pp. 417–441, 1999
  57. High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 3, pp. 265–281, 1999
  58. Hierarchical test generation and design for testability methods for ASPPs and ASIPs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 3, pp. 357–370, 1999
  59. Wavesched: a novel scheduling technique for control-flow intensive designs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 5, pp. 505–523, 1999
  60. Register transfer level power optimization with emphasis on glitch analysis and reduction
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 8, pp. 1114–1131, 1999
  61. Controller-based power management for control-flow intensive designs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 10, pp. 1496–1508, 1999
  62. FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 11, pp. 1577–1594, 1999
  63. A low overhead design for testability and test generation technique for core-based systems-on-a-chip
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 11, pp. 1661–1676, 1999
  64. High-level synthesis of low-power control-flow intensive circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 12, pp. 1715–1729, 1999
  65. Safety and reliability driven task allocation in distributed systems
    IEEE Transactions on Parallel and Distributed Systems, vol. 10, no. 3, pp. 238–251, 1999
  66. Power management in high-level synthesis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 1, pp. 7–15, 1999
  67. COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 1, pp. 92–104, 1999
  68. Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 4, pp. 608–619, 1998
  69. A design-for-testability technique for register-transfer level circuits using control/data flow extraction
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 8, pp. 706–723, 1998
  70. COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 10, pp. 900–919, 1998
  71. MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 10, pp. 920–935, 1998
  72. High-level test synthesis: a survey
    Integration, the VLSI Journal, vol. 26, no. 1-2, pp. 79–99, 1998
  73. Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 9, pp. 1001–1014, 1997
  74. SCALP: an iterative-improvement-based low-power data path synthesis system
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 11, pp. 1260–1277, 1997
  75. Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 12, pp. 1514–1521, 1997
  76. Graceful degradation in algorithm-based fault tolerant multiprocessor systems
    IEEE Transactions on Parallel and Distributed Systems, vol. 8, no. 2, pp. 137–153, 1997
  77. Analysis and randomized design of algorithm-based fault tolerant multiprocessor systems under an extended model
    IEEE Transactions on Parallel and Distributed Systems, vol. 8, no. 7, pp. 757–768, 1997
  78. Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 2, pp. 228–243, 1996
  79. A totally self-checking checker for a parallel unordered coding scheme
    IEEE Transactions on Computers, vol. 43, no. 4, pp. 490–495, 1994
  80. Algorithm-based fault tolerance for FFT networks
    IEEE Transactions on Computers, vol. 43, no. 7, pp. 849–854, 1994
  81. Partitioned encoding schemes for algorithm-based fault tolerance in massively parallel systems
    IEEE Transactions on Parallel and Distributed Systems, vol. 5, no. 6, pp. 649–653, 1994
  82. Design of algorithm-based fault-tolerant multiprocessor systems for concurrent error detection and fault diagnosis
    IEEE Transactions on Parallel and Distributed Systems, vol. 5, no. 10, pp. 1099–1106, 1994
  83. Synthesis of algorithm-based fault-tolerant systems from dependence graphs
    IEEE Transactions on Parallel and Distributed Systems, vol. 4, no. 8, pp. 864–874, 1993
  84. Optimal design of checks for error detection and location in fault-tolerant multiprocessor systems
    IEEE Transactions on Computers, vol. 42, no. 7, pp. 780–793, 1993
  85. Diagnosability and diagnosis of algorithm-based fault-tolerant systems
    IEEE Transactions on Computers, vol. 42, no. 8, pp. 924–937, 1993
  86. Fault detection in CVS parity trees with application to strongly self-checking parity and two-rail checkers
    IEEE Transactions on Computers, vol. 42, no. 2, pp. 179–189, 1993
  87. Design and synthesis of self-checking VLSI circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 6, pp. 878–887, 1993
  88. Design of C-testable DCVS binary array dividers
    IEEE Journal of Solid-State Circuits, vol. 26, no. 2, pp. 134–141, 1991
  89. Robustly testable static CMOS parity trees derived from binary decision diagrams
    IEEE Journal of Solid-State Circuits, vol. 26, no. 11, pp. 1728–1733, 1991
  90. Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 1, pp. 136–143, 1991
  91. A new transition count method for testing of logic circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 3, pp. 407–410, 1991
  92. Design of robustly testable combinational logic circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 8, pp. 1036–1048, 1991
  93. Easily testable gate-level and DCVS multipliers
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 7, pp. 932–942, 1991
  94. Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 3, pp. 332–336, 1990
  95. A new class of symmetric error correcting/unidirectional error detecting codes
    Computers & Mathematics with Applications, vol. 19, no. 5, pp. 95–104, 1990
  96. Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring
    Computers & Electrical Engineering, vol. 16, no. 3, pp. 115–124, 1990
  97. Testing of multiple-output domino logic (MODL) CMOS circuits
    IEEE Journal of Solid-State Circuits, vol. 25, no. 3, pp. 800–805, 1990
  98. Testing of zipper CMOS logic circuits
    IEEE Journal of Solid-State Circuits, vol. 25, no. 3, pp. 877–880, 1990
  99. Testing of differential cascode voltage switch one-count generators
    IEEE Journal of Solid-State Circuits, vol. 25, no. 1, pp. 246–253, 1990
  100. Comments on 'A MOS implementation of totally self-checking checker for the 1-out-of-3 code'
    IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1470–1471, 1989
  101. Robust testing of CMOS logic circuits
    Computers & Electrical Engineering, vol. 15, no. 1, pp. 19–28, 1989
  102. Separable codes for detecting unidirectional errors
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 5, pp. 571–574, 1989
  103. A totally self-checking checker for Borden's code
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 7, pp. 731–736, 1989
  104. A universal test set for CMOS circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 5, pp. 590–597, 1988
  105. Testing for multiple faults in domino-CMOS logic circuits
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 1, pp. 109–116, 1988
  106. Multiple stuck-open fault detection in CMOS logic circuits
    IEEE Transactions on Computers, vol. 37, no. 4, pp. 426–432, 1988
  107. Techniques for efficiently implementing totally self-checking checkers in MOS technology
    Computers & Mathematics with Applications, vol. 13, no. 5-6, pp. 555–566, 1987