Paul D. Franzon

Personal Home Page

http://www.ece.ncsu.edu/erl/faculty/paul_data/Mar02/index.htm

Articles in Scholarly Journals [Incomplete List]

  1. Uniformity analysis of wafer scale sub-25nm wide nanowire array nanoimprint mold fabricated by PEDAL process
    Microelectronic Engineering, vol. 84, no. 5-8, pp. 1523–1527, 2007
  2. Fully Integrated AC Coupled Interconnect Using Buried Bumps
    IEEE Transactions on Advanced Packaging, vol. 30, no. 2, pp. 191–199, 2007
  3. SOI CMOS Implementation of a Multirate PSK Demodulator for Space Communications
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 2, pp. 420–431, 2007
  4. Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 2, pp. 231–236, 2007
  5. Deterministic Nanowire Fanout and Interconnect Without Any Critical Translational Alignment
    IEEE Transactions On Nanotechnology, vol. 5, no. 4, pp. 356–361, 2006
  6. 3 Gb/s AC Coupled Chip-to-Chip Communication Using a Low Swing Pulse Receiver
    IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 287–296, 2006
  7. Physically based molecular device model in a transient circuit simulator
    Chemical Physics, vol. 326, no. 1, pp. 188–196, 2006
  8. Journal of the American Chemical Society, vol. 128, no. 45, pp. 14537–14541, 2006
  9. An Engineered Virus as a Scaffold for Three-Dimensional Self-Assembly on the Nanoscale
    Small, vol. 1, no. 7, pp. 702–706, 2005
  10. Fabrication of wafer scale, aligned sub-25nm nanowire and nanowire templates using planar edge defined alternate layer process
    Physica E: Low-dimensional Systems and Nanostructures, vol. 28, no. 2, pp. 107–114, 2005
  11. Scaling constraints in nanoelectronic random-access memories
    Nanotechnology, vol. 16, no. 10, pp. 2251–2260, 2005
  12. Demystifying 3D ICs: The Pros and Cons of Going Vertical
    IEEE Design and Test of Computers, vol. 22, no. 6, pp. 498–510, 2005
  13. CAD Flows for Chip-Package Coverification
    IEEE Transactions on Advanced Packaging, vol. 28, no. 1, pp. 96–101, 2005
  14. Optimal Chip-Package Codesign for High-Performance DSP
    IEEE Transactions on Advanced Packaging, vol. 28, no. 2, pp. 288–297, 2005
  15. An Electronically Tunable Microstrip Bandpass Filter Using Thin-Film Barium–Strontium–Titanate (BST) Varactors
    IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 9, pp. 2707–2712, 2005
  16. Chip-Package Co-Implementation of a Triple DES Processor
    IEEE Transactions on Advanced Packaging, vol. 27, no. 1, pp. 194–202, 2004
  17. Buried Bump and AC Coupled Interconnection Technology
    IEEE Transactions on Advanced Packaging, vol. 27, no. 1, pp. 121–125, 2004
  18. A "defect level versus cost" system tradeoff for electronics manufacturing
    IEEE Transactions on Electronics Packaging Manufacturing, vol. 27, no. 1, pp. 67–76, 2004
  19. The Design and Characterization of a Novel Piezoelectric Transducer-Based Linear Motor
    IEEE/ASME Transactions on Mechatronics, vol. 9, no. 2, pp. 392–398, 2004
  20. Causal Reduced-Order Modeling of Distributed Structures in a Transient Circuit Simulator
    IEEE Transactions on Microwave Theory and Techniques, vol. 52, no. 9, pp. 2207–2214, 2004
  21. AC Coupled Interconnect for Dense 3-D ICs
    IEEE Transactions on Nuclear Science, vol. 51, no. 5, pp. 2156–2160, 2004
  22. Clustering Effects on Discontinuous Gold Film NanoCells
    Journal of Nanoscience and Nanotechnology, vol. 4, no. 7, pp. 907–917, 2004
  23. Journal of the American Chemical Society, vol. 125, no. 43, pp. 13279–13283, 2003
  24. Molecular electronics: from devices and interconnect to circuits and architecture
    Proceedings of the IEEE, vol. 9, no. 11, pp. 1940–1957, 2003
  25. Novel hardware architecture for fast address lookups
    IEEE Communications Magazine, vol. 40, no. 11, pp. 66–71, 2002
  26. Nanocell logic gates for molecular computing
    IEEE Transactions On Nanotechnology, vol. 1, no. 2, pp. 100–109, 2002
  27. Phase synchronization of micro-mirror arrays using elastic linkages
    Sensors and Actuators A: Physical, vol. 95, no. 1, pp. 55–60, 2001
  28. High frequency loss and electromagnetic field distribution for striplines and microstrips [MCM packages]
    IEEE Transactions on Advanced Packaging, vol. 22, no. 1, pp. 16–25, 1999
  29. A review of 3-D packaging technology
    IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, vol. 21, no. 1, pp. 2–14, 1998
  30. The Journal of VLSI Signal Processing, vol. 16, no. 2/3, pp. 131–147, 1997
  31. Experimental characterization of transmission lines in thin-film multichip modules
    IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, vol. 19, no. 1, pp. 122–126, 1996
  32. Simulation of high speed interconnects using a convolution-based hierarchical packaging simulator
    IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, vol. 18, no. 1, pp. 74–82, 1995
  33. System design optimization for MCM-D/flip-chip
    IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, vol. 18, no. 4, pp. 620–627, 1995
  34. Energy consumption modeling and optimization for SRAM's
    IEEE Journal of Solid-State Circuits, vol. 30, no. 5, pp. 571–579, 1995
  35. Energy control and accurate delay estimation in the design of CMOS buffers
    IEEE Journal of Solid-State Circuits, vol. 29, no. 9, pp. 1150–1153, 1994
  36. Delay and reflection noise macromodeling for signal integrity management of PCBs and MCMs
    IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, vol. 17, no. 1, pp. 15–21, 1994
  37. A layout-driven yield predictor and fault generator for VLSI
    IEEE Transactions on Semiconductor Manufacturing, vol. 6, no. 1, pp. 77–82, 1993
  38. Method for automated waveform analysis of transient responses in digital circuits
    Electronics Letters, vol. 29, no. 8, p. 681, 1993
  39. Comparison of methods for determining the capacitance of planar transmission lines with application to multichip module characterization
    IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 16, no. 3, pp. 247–252, 1993
  40. Comments on 'An accurate measurement technique for line properties, junction effects, and dielectric and magnetic parameters' (and reply)
    IEEE Transactions on Microwave Theory and Techniques, vol. 40, no. 2, pp. 410–411, 1992
  41. Experimental electrical characterization of interconnects and discontinuities in high-speed digital systems
    IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 14, no. 4, pp. 761–765, 1991
  42. Modelling interconnect yield in reconfigurable circuits
    Electronics Letters, vol. 25, no. 18, p. 1225, 1989
  43. FIR digital filters for high sample rate applications
    IEEE Communications Magazine, vol. 25, no. 7, pp. 62–72, 1987