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Articles in Scholarly Journals [Incomplete List]

1. IEEE Transactions on Consumer Electronics, vol. 53, no. 3, pp. 1130–1137, 2007
2. Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC
   IEEE Transactions on Circuits and Systems for Video Technology, vol. 17, no. 2, pp. 242–247, 2007
3. 124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory
   IEEE Transactions on Circuits and Systems for Video Technology, vol. 17, no. 4, pp. 398–406, 2007
4. Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
   IEEE Transactions on Circuits and Systems for Video Technology, vol. 17, no. 5, pp. 568–577, 2007
5. Word-Level Parallel Architecture of JPEG 2000 Embedded Block Coding Decoder
   IEEE Transactions on Multimedia, vol. 9, no. 6, pp. 1103–1112, 2007
6. System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering
   IEEE Transactions on Signal Processing, vol. 54, no. 10, pp. 4004–4014, 2006
7. Memory Efficient JPEG 2000 Architecture With Stripe Pipeline Scheduling
   IEEE Transactions on Signal Processing, vol. 54, no. 12, pp. 4807–4816, 2006
8. One-Pass Computation-Aware Motion Estimation With Adaptive Search Strategy
   IEEE Transactions on Multimedia, vol. 8, no. 4, pp. 698–706, 2006
9. High-Performance JPEG 2000 Encoder With Rate-Distortion Optimization
   IEEE Transactions on Multimedia, vol. 8, no. 4, pp. 645–653, 2006
10. Precompression Quality-Control Algorithm for JPEG 2000
    IEEE Transactions on Image Processing, vol. 15, no. 11, pp. 3279–3293, 2006
11. Level C+ Data Reuse Scheme for Motion Estimation With Corresponding Coding Orders
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 4, pp. 553–558, 2006
12. Analysis and Complexity Reduction of Multiple Reference Frames Motion Estimation in H.264/AVC
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 4, pp. 507–522, 2006
13. Analysis and Architecture Design of an HDTV720p 30 Frames/s H.264/AVC Encoder
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 6, pp. 673–688, 2006
14. Joint Prediction Algorithm and Architecture for Stereo Video Hybrid Coding Systems
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 11, pp. 1324–1337, 2006
15. Analysis and Architecture Design of Variable Block-Size Motion Estimation for H.264/AVC
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 3, pp. 578–593, 2006
16. Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 9, pp. 832–836, 2006
17. Algorithm analysis and architecture design for HDTV applications
    IEEE Circuits and Devices Magazine, vol. 22, no. 3, pp. 22–31, 2006
18. Platform-Based MPEG-4 SOC Design for Video Communications
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 42, no. 1, pp. 7–19, 2006
19. Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems
    The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 42, no. 3, pp. 241–255, 2006
20. Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
    The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 42, no. 3, pp. 297–320, 2006
21. Interactive Content-aware Video Streaming System with Fine Granularity Scalability
    The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 44, no. 1-2, pp. 117–134, 2006
22. VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 40, no. 2, pp. 175–188, 2005
23. VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 40, no. 3, pp. 343–353, 2005
24. Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 41, no. 1, pp. 35–47, 2005
25. An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System
    The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 41, no. 2, pp. 183–191, 2005
26. Feature-Based Error Concealment for Object-Based Video
    IEICE Transactions on Communications, vol. E88-B, no. 6, pp. 2616–2626, 2005
27. Hardware architecture design of video compression for multimedia communication systems
    IEEE Communications Magazine, vol. 43, no. 8, pp. 123–131, 2005
28. Special Issue on Advances in Video Coding and Delivery
    Proceedings of the IEEE, vol. 93, no. 1, pp. 3–5, 2005
29. Advances in Hardware Architectures for Image and Video Coding—A Survey
    Proceedings of the IEEE, vol. 93, no. 1, pp. 184–197, 2005
30. Fast Decomposition of Filterbanks for the State-of-the-Art Audio Coding
    IEEE Signal Processing Letters, vol. 12, no. 10, pp. 693–696, 2005
31. Analysis, Fast Algorithm, and VLSI Architecture Design for H.264/AVC Intra Frame Coder
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 3, pp. 378–401, 2005
32. Generic RAM-Based Architectures for Two-Dimensional Discrete Wavelet Transform With Line-Based Method
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 7, pp. 910–920, 2005
33. Parallel Embedded Block Coding Architecture for JPEG 2000
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 9, pp. 1086–1097, 2005
34. Partial-Result-Reuse Architecture and Its Design Technique for Morphological Operations With Flat Structuring Elements
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 9, pp. 1156–1169, 2005
35. Video de-interlacing by adaptive 4-field global/local motion compensated approach
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 12, pp. 1569–1582, 2005
36. Analysis and VLSI Architecture for 1-D and 2-D Discrete Wavelet Transform
    IEEE Transactions on Signal Processing, vol. 53, no. 4, pp. 1575–1586, 2005
37. Nonparametric smoothing of interferometric height maps using confidence values
    Optical Engineering, vol. 43, no. 4, p. 866, 2004
38. Flipping Structure: An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
    IEEE Transactions on Signal Processing, vol. 52, no. 4, pp. 1080–1089, 2004
39. A low complexity design of psycho-acoustic model for MPEG-2/4 advanced audio coding
    IEEE Transactions on Consumer Electronics, vol. 50, no. 4, pp. 1209–1217, 2004
40. Global Elimination Algorithm and Architecture Design for Fast Block Matching Motion Estimation
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 14, no. 6, pp. 898–907, 2004
41. Fast Video Segmentation Algorithm With Shadow Cancellation, Global Motion Compensation, and Adaptive Threshold Techniques
    IEEE Transactions on Multimedia, vol. 6, no. 5, pp. 732–748, 2004
42. Power-Efficient FIR Filter Architecture Design for Wireless Embedded System
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 51, no. 1, pp. 21–25, 2004
43. Motion adaptive interpolation with horizontal motion detection for deinterlacing
    IEEE Transactions on Consumer Electronics, vol. 49, no. 4, pp. 1256–1265, 2003
44. Error concealment algorithm using interested direction for JPEG 2000 image transmission
    IEEE Transactions on Consumer Electronics, vol. 49, no. 4, pp. 1395–1401, 2003
45. Predictive line search: an efficient motion estimation algorithm for MPEG-4 encoding systems on multimedia processors
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 1, pp. 111–117, 2003
46. Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 3, pp. 219–230, 2003
47. Predictive watershed: a fast watershed algorithm for video segmentation
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 5, pp. 453–461, 2003
48. Efficient moving object segmentation algorithm using background registration technique
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 12, no. 7, pp. 577–586, 2002
49. VLSI architecture design of MPEG-4 shape coding
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 12, no. 9, pp. 741–751, 2002
50. Low-delay and error-robust wireless video transmission for video communications
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 12, no. 12, pp. 1049–1058, 2002
51. A digital signal processor with programmable correlator array architecture for third generation wireless communication system
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 12, pp. 1110–1120, 2001
52. An efficient architecture for two-dimensional discrete wavelet transform
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 4, pp. 536–545, 2001
53. A novel low-power full-search block-matching motion-estimation design for H.263+
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 7, pp. 890–897, 2001
54. CDSP: an application-specific digital signal processor for third generation wireless communications
    IEEE Transactions on Consumer Electronics, vol. 47, no. 3, pp. 672–677, 2001
55. The Journal of VLSI Signal Processing, vol. 28, no. 3, pp. 151–163, 2001
56. The Journal of VLSI Signal Processing, vol. 29, no. 3, pp. 255–265, 2001
57. System design consideration for digital wheelchair controller
    IEEE Transactions on Industrial Electronics, vol. 47, no. 4, pp. 898–907, 2000
58. A novel architecture of inverse quantization and multichannel processing for MPEG-2 audio decoding
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 1, pp. 75–78, 2000
59. A single-chip CMOS APS camera with direct frame difference output
    IEEE Journal of Solid-State Circuits, vol. 34, no. 10, pp. 1415–1418, 1999
60. A LOG-EXP still image compression chip design
    IEEE Transactions on Consumer Electronics, vol. 45, no. 3, pp. 812–819, 1999
61. A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 2, pp. 124–127, 1998
62. A block shifting method for reduction of blocking effects in subband/wavelet image coding
    IEEE Transactions on Consumer Electronics, vol. 44, no. 1, pp. 170–177, 1998
63. VLSI implementation of visual block pattern truncation coding
    IEEE Transactions on Consumer Electronics, vol. 44, no. 3, pp. 490–499, 1998
64. A novel MPEG-2 audio decoder with efficient data arrangement and memory configuration
    IEEE Transactions on Consumer Electronics, vol. 43, no. 3, pp. 598–604, 1997
65. An I-phone system design and implementation with a portable speech coding coprocessor
    IEEE Transactions on Consumer Electronics, vol. 43, no. 4, pp. 1262–1269, 1997
66. A bit-level pipelined VLSI architecture for the running order algorithm
    IEEE Transactions on Signal Processing, vol. 45, no. 8, pp. 2140–2144, 1997
67. A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 7, no. 3, pp. 459–467, 1997
68. Error concealment of lost motion vectors with overlapped motion compensation
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 7, no. 3, pp. 560–563, 1997
69. IMMUNOLGY: Reuse of B Lymphocyte in Germinal Centers
    Science, vol. 278, no. 5336, pp. 238–239, 1997
70. Scalable implementation scheme for multirate FIR filters and its application in efficient design of subband filter banks
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 6, no. 4, pp. 407–410, 1996
71. VLSI implementation of a selective median filter
    IEEE Transactions on Consumer Electronics, vol. 42, no. 1, pp. 33–42, 1996
72. IC design of an adaptive Viterbi decoder
    IEEE Transactions on Consumer Electronics, vol. 42, no. 1, pp. 52–62, 1996
73. A novel video signal processor with programmable data arrangement and efficient memory configuration
    IEEE Transactions on Consumer Electronics, vol. 42, no. 3, pp. 526–534, 1996
74. Investigation of a visual telephone prototyping on personal computers
    IEEE Transactions on Consumer Electronics, vol. 42, no. 3, pp. 750–759, 1996
75. A multimedia video conference system: using region base hybrid coding
    IEEE Transactions on Consumer Electronics, vol. 42, no. 3, pp. 781–786, 1996
76. Efficient hybrid tree/linear array architectures for block-matching motion estimation algorithms
    IEE Proceedings - Vision, Image, and Signal Processing, vol. 143, no. 4, p. 217, 1996
77. A 32-bit logarithmic number system processor
    Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 14, no. 3, pp. 311–319, 1996
78. Pipeline interleaving design for FIR, IIR, and FFT array processors
    Journal of VLSI Signal Processing, vol. 10, no. 3, pp. 275–293, 1995
79. Concurrent error detection in array multipliers by BIDO
    IEE Proceedings - Computers and Digital Techniques, vol. 142, no. 6, p. 425, 1995
80. An MPEG audio decoder chip
    IEEE Transactions on Consumer Electronics, vol. 41, no. 1, pp. 89–96, 1995
81. A single-chip Viterbi decoder for a binary convolutional code using an adaptive algorithm
    IEEE Transactions on Consumer Electronics, vol. 41, no. 1, pp. 150–159, 1995
82. High throughput CORDIC-based systolic array design for the discrete cosine transform
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 3, pp. 218–225, 1995
83. A new block-matching criterion for motion estimation and its implementation
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 3, pp. 231–236, 1995
84. Vector quantization using tree-structured self-organizing feature maps
    IEEE Journal on Selected Areas in Communications, vol. 12, no. 9, pp. 1594–1599, 1994
85. Accuracy improvement and cost reduction of 3-step search block matching algorithm for video coding
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 4, no. 1, pp. 88–90, 1994
86. A high quality MC-OBTC Codec for video signal processing
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 4, no. 1, pp. 92–98, 1994
87. Parallel architectures for 3-step hierarchical search block-matching algorithm
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 4, no. 4, pp. 407–416, 1994
88. One-dimensional full search motion estimation algorithm for video coding
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 4, no. 5, pp. 504–509, 1994
89. Rate-optimal DSP synthesis by pipeline and minimum unfolding
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, no. 1, pp. 81–88, 1994
90. Excitonic mechanism of athermal halogen atom desorption from NaBr, KBr and RbBr
    Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, vol. 91, no. 1-4, pp. 614–618, 1994
91. Cache vector quantisation algorithm in video compression
    Electronics Letters, vol. 29, no. 16, p. 1423, 1993
92. An efficient and simple VLSI tree architecture for motion estimation algorithms
    IEEE Transactions on Signal Processing, vol. 41, no. 2, pp. 889–900, 1993
93. A real-time video signal processing chip
    IEEE Transactions on Consumer Electronics, vol. 39, no. 2, pp. 82–92, 1993
94. Concurrent error-detectable butterfly chip for real-time FFT processing through time redundancy
    IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 537–547, 1993
95. Design and analysis of VLSI-based arithmetic arrays with error correction
    International Journal of Electronics, vol. 72, no. 2, pp. 253–271, 1992
96. A motion estimator for low bit-rate video codec
    IEEE Transactions on Consumer Electronics, vol. 38, no. 2, pp. 60–69, 1992
97. DCT-based interframe coding for video codec
    Electronics Letters, vol. 28, no. 4, p. 411, 1992
98. ROM-based special purpose multiplication and its applications
    Electronics Letters, vol. 28, no. 8, p. 718, 1992
99. ASG: Automatic schematic generator
    Integration, the VLSI Journal, vol. 11, no. 1, pp. 11–27, 1991
100. An efficient parallel motion estimation algorithm for digital image processing
     IEEE Transactions on Circuits and Systems for Video Technology, vol. 1, no. 4, pp. 378–385, 1991
101. Fast execution for circuit consistency verification
     Integration, the VLSI Journal, vol. 4, no. 3, pp. 239–262, 1986
102. VLSI-based array dividers with concurrent error detection
     International Journal of Electronics, vol. 78, no. 6, pp. 1139–1148, 1985