Chong-Min Kyung

Articles in Scholarly Journals [Incomplete List]

  1. Data reuse algorithm for multiple reference frame motion estimation
    Electronics Letters, vol. 43, no. 7, p. 382, 2007
  2. Enhancing performance of HW/SW cosimulation and coemulation by reducing communication overhead
    IEEE Transactions on Computers, vol. 55, no. 2, pp. 125–136, 2006
  3. PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 1935–1949, 2006
  4. Journal of Circuits, Systems, and Computers, vol. 15, no. 2, p. 263, 2006
  5. Journal of Circuits, Systems, and Computers, vol. 14, no. 1, p. 137, 2005
  6. Performance-Driven Event-Based Synchronization for Multi-FPGA Simulation Accelerator With Event Time-Multiplexing Bus
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 9, pp. 1444–1456, 2005
  7. ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 7, pp. 861–864, 2005
  8. C-Specimen Fracture Toughness Testing: Effect of Side Grooves and ? Factor
    Journal of Pressure Vessel Technology, vol. 126, no. 3, p. 293, 2004
  9. CeRA: a router for symmetrical FPGAs based on exact routing density evaluation
    IEEE Transactions on Computers, vol. 53, no. 7, pp. 829–842, 2004
  10. TPartition: testbench partitioning for hardware-accelerated functional verification
    IEEE Design and Test of Computers, vol. 21, no. 6, pp. 484–493, 2004
  11. Memory reduction by intermediate result value encoding for content-based classification
    Electronics Letters, vol. 40, no. 17, p. 1041, 2004
  12. Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture
    Microprocessors and Microsystems, vol. 28, no. 5-6, pp. 341–350, 2004
  13. Interface synthesis between software chip model and target board
    Journal of Systems Architecture, vol. 48, no. 1-3, pp. 49–57, 2002
  14. Conforming block inversion for low power memory
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 1, pp. 15–19, 2002
  15. Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 3, pp. 240–252, 2002
  16. MetaCore: an application-specific programmable DSP development system
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 2, pp. 173–183, 2000
  17. Path-based branch prediction using signature analysis
    Microprocessors and Microsystems, vol. 23, no. 8-9, pp. 527–536, 1999
  18. Control signal layout ordering scheme minimising cross-coupling effect in deep-submicrometre datapath design
    Electronics Letters, vol. 35, no. 18, p. 1542, 1999
  19. Synthesis of application specific instructions for embedded DSP software
    IEEE Transactions on Computers, vol. 48, no. 6, pp. 603–614, 1999
  20. DIVA: dual-issue VLIW architecture with media instructions for image processing
    IEEE Transactions on Consumer Electronics, vol. 45, no. 1, pp. 192–202, 1999
  21. Digital signal processor with efficient RGB interpolation and histogram accumulation
    IEEE Transactions on Consumer Electronics, vol. 44, no. 4, pp. 1389–1395, 1998
  22. Datapath layout optimisation using genetic algorithm and simulated annealing
    IEE Proceedings - Computers and Digital Techniques, vol. 145, no. 2, p. 135, 1998
  23. Radix-4 multiplier with regular layout structure
    Electronics Letters, vol. 34, no. 15, p. 1446, 1998
  24. Journal of Circuits, Systems, and Computers, vol. 7, no. 4, p. 301, 1997
  25. Bypassing omega network for high speed packet switching
    Electronics Letters, vol. 32, no. 25, p. 2301, 1996
  26. Efficient state encoding algorithm based on hypercube construction
    IEE Proceedings - Computers and Digital Techniques, vol. 142, no. 3, p. 225, 1995
  27. Two complementary approaches for microcode bit optimization
    IEEE Transactions on Computers, vol. 43, no. 2, pp. 234–239, 1994
  28. New hardware scheme supporting precise exception handling for out-of-order execution
    Electronics Letters, vol. 30, no. 1, p. 16, 1994
  29. State assignment in finite state machines for minimal switching power consumption
    Electronics Letters, vol. 30, no. 8, p. 627, 1994
  30. Design of compact static CMOS carry look-ahead adder using recursive output property
    Electronics Letters, vol. 29, no. 9, p. 794, 1993
  31. FAMOS: an efficient scheduling algorithm for high-level synthesis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 10, pp. 1437–1448, 1993
  32. Circuit placement on arbitrarily shaped regions using the self-organization principle
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 7, pp. 844–854, 1992
  33. HALO: an efficient global placement strategy for standard cells
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 8, pp. 1024–1031, 1992
  34. PYSHA: a shadow-testing acceleration scheme for ray tracing
    Computer-Aided Design, vol. 24, no. 2, pp. 93–104, 1992
  35. Adaptive cluster growth: a new algorithm for circuit placement in rectilinear regions
    Computer-Aided Design, vol. 24, no. 1, pp. 27–35, 1992
  36. Analytic approach to three layer channel routing
    Electronics Letters, vol. 28, no. 18, p. 1738, 1992
  37. Three-step pin assignment algorithm for building block layout
    Electronics Letters, vol. 28, no. 20, p. 1882, 1992
  38. Finding optimal module orientations in macrocell placement
    Electronics Letters, vol. 27, no. 10, p. 804, 1991
  39. Module orientation algorithm using reconstruction of nets and mean field annealing
    Electronics Letters, vol. 27, no. 13, p. 1198, 1991
  40. Fast frame-to-frame interpolation technique for scenes containing moving objects
    Electronics Letters, vol. 27, no. 20, p. 1788, 1991
  41. An analytic algorithm for global circuit placement
    Integration, the VLSI Journal, vol. 11, no. 2, pp. 191–204, 1991
  42. Optimal encoding of microcommands in microprogrammed processors
    Electronics Letters, vol. 26, no. 6, p. 393, 1990
  43. Algorithm for optimal layouts of CMOS complex logic modules
    Electronics Letters, vol. 26, no. 17, p. 1388, 1990
  44. An efficient algorithm for optimal PLA folding
    Integration, the VLSI Journal, vol. 9, no. 3, pp. 271–285, 1990
  45. Hybrid shadow testing scheme for ray tracing
    Computer-Aided Design, vol. 21, no. 1, pp. 38–48, 1989
  46. An efficient algorithm for two- and three-dimensional IC floor planning
    International Journal of Circuit Theory and Applications, vol. 16, no. 4, pp. 425–445, 1988
  47. New hardware architecture for fast raster image generation
    Electronics Letters, vol. 24, no. 7, p. 382, 1988
  48. Three-step heuristic algorithm for optimal PLA column folding
    Electronics Letters, vol. 24, no. 17, p. 1088, 1988
  49. A heuristic standard cell placement algorithm using constrained multistage graph model
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 11, pp. 1205–1214, 1988
  50. Two-dimensional impurity profiling near the mask edge using anodisation
    Electronics Letters, vol. 21, no. 14, p. 587, 1985