Stephen A. Edwards

Personal Home Page

http://www.cs.columbia.edu/~sedwards/

Articles in Scholarly Journals [Incomplete List]

  1. Optimizing Sequential Cycles Through Shannon Decomposition and Retiming
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3, pp. 456–467, 2007
  2. Code Generation in the Columbia Esterel Compiler
    EURASIP Journal on Embedded Systems, vol. 2007, Article ID 52651, 31 pages, 2007
  3. Guest Editorial
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 5, pp. 741–742, 2006
  4. SHIM: A Deterministic Model for Heterogeneous Embedded Systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 8, pp. 854–867, 2006
  5. Efficient code generation from SHIM models
    ACM SIGPLAN Notices, vol. 41, no. 7, p. 125, 2006
  6. The Challenges of Synthesizing Hardware from C-Like Languages
    IEEE Design and Test of Computers, vol. 23, no. 5, pp. 375–386, 2006
  7. Compiling Esterel into Static Discrete-Event Code
    Electronic Notes in Theoretical Computer Science, vol. 153, no. 4, pp. 117–131, 2006
  8. A Domain-Specific Language for Generating Dataflow Analyzers
    Electronic Notes in Theoretical Computer Science, vol. 164, no. 2, pp. 103–119, 2006
  9. NDL
    ACM SIGPLAN Notices, vol. 39, no. 7, p. 30, 2004
  10. Generating fast code from concurrent program dependence graphs
    ACM SIGPLAN Notices, vol. 39, no. 7, p. 175, 2004
  11. Tutorial
    ACM Transactions on Design Automation of Electronic Systems, vol. 8, no. 2, pp. 141–187, 2003
  12. The synchronous languages 12 years later
    Proceedings of the IEEE, vol. 91, no. 1, pp. 64–83, 2003
  13. The semantics and execution of a synchronous block-diagram language
    Science of Computer Programming, 2002
  14. PrefaceVolume 65, Issue 5
    Electronic Notes in Theoretical Computer Science, vol. 65, no. 5, pp. 1–2, 2002
  15. An Esterel compiler for large control-dominated systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 2, pp. 169–183, 2002
  16. Design of embedded systems: formal models, validation, and synthesis
    Proceedings of the IEEE, vol. 85, no. 3, pp. 366–390, 1997