Articles in Scholarly Journals [Incomplete List]

1. Map construction of unknown graphs by multiple agents?
   Theoretical Computer Science, vol. 385, no. 1-3, pp. 34–48, 2007
2. Characterization, testing and reconfiguration of faults in mesh networks
   Integration, the VLSI Journal, vol. 40, no. 4, pp. 525–535, 2007
3. Enhancing peer-to-peer systems through redundancy
   IEEE Journal on Selected Areas in Communications, vol. 25, no. 1, pp. 15–24, 2007
4. Testing Analog and Mixed-Signal Circuits With Built-In Hardware—A New Approach
   IEEE Transactions on Instrumentation and Measurement, vol. 56, no. 3, pp. 840–855, 2007
5. Flagellin Suppresses the Inflammatory Response and Enhances Bacterial Clearance in a Murine Model of Pseudomonas aeruginosa Keratitis
   Infection and Immunity, vol. 76, no. 1, pp. 89–96, 2007
6. Parallel Processing Letters, vol. 16, no. 1, p. 63, 2006
7. Timing Recovery With Frequency Offset and Random Walk: Cramer–Rao Bound and a Phase-Locked Loop Postprocessor
   IEEE Transactions on Communications, vol. 54, no. 10, pp. 1896–1896, 2006
8. Timing Recovery With Frequency Offset and Random Walk: Cramér–Rao Bound and a Phase- Locked Loop Postprocessor
   IEEE Transactions on Communications, vol. 54, no. 11, pp. 2004–2013, 2006
9. Progress and Location Based Localized Power Aware Routing for ad hoc and Sensor Wireless Networks
   International Journal of Distributed Sensor Networks, vol. 2, no. 2, pp. 147–159, 2006
10. A hybrid randomized protocol for RFID tag identification
    Sensor Review, vol. 26, no. 2, pp. 147–154, 2006
11. Localized routing with guaranteed delivery and a realistic physical layer in wireless sensor networks
    Computer Communications, vol. 29, no. 13-14, pp. 2550–2555, 2006
12. Greedy localized routing for maximizing probability of delivery in wireless ad hoc networks with a realistic physical layer
    Journal of Parallel and Distributed Computing, vol. 66, no. 4, pp. 499–506, 2006
13. Physical layer impact on the design and performance of routing and broadcasting protocols in ad hoc and sensor networks
    Computer Communications, vol. 28, no. 10, pp. 1138–1151, 2005
14. A parallel genetic algorithm for identifying faults in large diagnosable systems
    International Journal of Parallel, Emergent and Distributed Systems, vol. 20, no. 2, pp. 113–125, 2005
15. Hop Count Optimal Position-Based Packet Routing Algorithms for Ad Hoc Wireless Networks With a Realistic Physical Layer
    IEEE Journal on Selected Areas in Communications, vol. 23, no. 6, pp. 1267–1275, 2005
16. Design guidelines for routing protocols in ad hoc and sensor networks with a realistic physical layer
    IEEE Communications Magazine, vol. 43, no. 3, pp. 101–106, 2005
17. On characterization of catastrophic faults in two-dimensional VLSI arrays
    Integration, the VLSI Journal, vol. 38, no. 2, pp. 267–281, 2004
18. On enumeration of catastrophic fault patterns
    Information Processing Letters, vol. 81, no. 4, pp. 209–212, 2002
19. Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links
    Integration, the VLSI Journal, vol. 30, no. 2, pp. 157–168, 2001
20. An improved testing scheme for catastrophic fault patterns
    Information Processing Letters, vol. 73, no. 5-6, pp. 199–206, 2000
21. Space compaction under generalized mergeability
    IEEE Transactions on Instrumentation and Measurement, vol. 47, no. 5, pp. 1283–1293, 1998
22. Syndrome Signature in Output Compaction for VLSI Built-in Self-Test
    VLSI Design, vol. 7, no. 2, pp. 191–201, 1998
23. Characterization of Catastrophic Faults in Reconfigurable Systolic Arrays
    VLSI Design, vol. 7, no. 2, pp. 143–150, 1998
24. On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy
    Integration, the VLSI Journal, vol. 20, no. 3, pp. 327–342, 1996
25. A note on isomorphic chordal rings
    Information Processing Letters, vol. 55, no. 6, pp. 339–341, 1995
26. On testing of sequential machines using circuit decomposition and stochastic modeling
    IEEE Transactions on Systems, Man, and Cybernetics, vol. 25, no. 3, pp. 489–504, 1995
27. Efficient construction of catastrophic patterns for VLSI reconfigurable arrays
    Integration, the VLSI Journal, vol. 15, no. 2, pp. 133–150, 1993
28. PROBABILISTIC FAULT LOCATION IN COMBINATIONAL LOGIC NETWORK USING CONCEPTS OF FAULT DISTANCE AND INPUT FEATURE
    Cybernetics and Systems, vol. 20, no. 5, pp. 385–399, 1989