A.-Y. Wu

An-Yeu (Andy) Wu received the B.S. degree from National Taiwan University in 1987, and the M.S. and Ph.D. degrees from the University of Maryland, College Park, in 1992 and 1995, respectively, all in electrical engineering. During 1987–1989, he served as a Signal Officer in the Army, Taipei, Taiwan, for his mandatory military service. From August 1995 to July 1996, he was a member of the technical staff at AT&T Bell Laboratories, Murray Hill, NJ, working on high-speed transmission IC designs. From 1996 to July 2000, he was in the Electrical Engineering Department of National Central University, Taiwan. He is currently an Associate Professor in the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taiwan. His research interests include low-power/high-performance VLSI architectures for DSP and communication applications, adaptive/multirate signal processing, and reconfigurable broadband access systems and architectures. Dr. Wu is currently serving as an Associate Editor for EURASIP Journal on Applied Signal Processing. He became the Associate Editor of the IEEE Transactions on Very Large-Scale Integration (VLSI) Systems in July 2003. He has served on the technical program committees of IEEE International Conferences such as ICIP, SiPS, AP-ASIC, SOC, and ISCAS.

Biography Updated on 12 August 2007

Articles in Scholarly Journals [Incomplete List]

  1. Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 2, pp. 236–240, 2007
  2. High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 9, pp. 911–915, 2006
  3. Area-Efficient VLSI Design of Reed–Solomon Decoder for 10GBase-LX4 Optical Communication Systems
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 11, pp. 1245–1249, 2006
  4. Multi-Symbol-Sliced Dynamically Reconfigurable Reed–Solomon Decoder Design Based on Unified Finite-Field Processing Element
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 5, pp. 489–500, 2006
  5. Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2385–2396, 2005
  6. Soft-Threshold-Based Multilayer Decision Feedback Equalizer (STM-DFE) Algorithm and VLSI Architecture
    IEEE Transactions on Signal Processing, vol. 53, no. 8, pp. 3325–3336, 2005
  7. Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, no. 2, pp. 57–60, 2004
  8. High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 218–226, 2004
  9. Editorial
    EURASIP Journal on Applied Signal Processing, vol. 2003, no. 13, pp. 1265–1267, 2003
  10. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems
    EURASIP Journal on Applied Signal Processing, vol. 2003, no. 13, pp. 1306–1316, 2003
  11. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 34, no. 3, pp. 251–259, 2003
  12. A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 9, pp. 589–601, 2003
  13. A Reduced-Complexity Fast Algorithm for Software Implementation of the IFFT/FFT in DMT Systems
    EURASIP Journal on Applied Signal Processing, vol. 2002, no. 9, pp. 961–974, 2002
  14. A unified view for vector rotational CORDIC algorithms and architectures based on angle quantization approach
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 49, no. 10, pp. 1442–1456, 2002
  15. Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 6, pp. 548–561, 2001
  16. Algorithm-based low-power transform coding architectures: the multirate approach
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 4, pp. 707–718, 1998
  17. Algorithm-based low-power and high-performance multimedia signal processing
    Proceedings of the IEEE, vol. 86, no. 6, pp. 1155–1202, 1998
  18. System architecture of an adaptive reconfigurable DSP computing engine
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 1, pp. 54–73, 1998
  19. Split Recursive Least-Squares: algorithms, architectures, and applications
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, no. 9, pp. 645–658, 1996