Yu-Hen Hu

Yu Hen Hu received the B.S.E.E. degree from National Taiwan University, Taiwan, in 1976. He received the M.S. and Ph.D. degrees both in electrical engineering from University of Southern California, Los Angeles, Calif, USA, in 1980 and 1982, respectively. Currently, he is a Professor at the Electrical and Computer Engineering Department of the University of Wisconsin-Madison, Wis, USA. Previously, he has been with the Electrical Engineering Department of the Southern Methodist University, Dallas, Tex, USA. Dr. Hu research interests include multimedia signal processing, design methodology, and implementation of signal processing algorithms and systems, sensor network and distributive signal processing algorithms, and neural network signal processing. He published more than 200 journal and conference papers and edited two books: Programmable Digital Signal Processors and Handbook of Neural Network Signal Processing. Dr. Hu is a Fellow of IEEE. He served as Associate Editor for IEEE Transactions on Signal Processing, IEEE Signal Processing Letters, Journal of VLSI Signal Processing, EURASIP Journal on Advances in Signal Processing. He served as Secretary of IEEE signal processing society, board of governors of IEEE neural network council, Chair of IEEE signal processing society, and neural network signal processing technical committee.

Biography Updated on 30 August 2007

Personal Home Page

http://www.engr.wisc.edu/ece/faculty/hu_yu.html

Articles in Scholarly Journals [Incomplete List]

  1. Numerically Convex Forms and Their Application in Gate Sizing
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 9, pp. 1637–1647, 2007
  2. Statistical Static Timing Analysis With Conditional Linear MAX/MIN Approximation and Extended Canonical Timing Model
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 6, pp. 1183–1191, 2006
  3. Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2437–2449, 2006
  4. Inform, involve, and interact- bring the society and its members together [from The Editor]
    IEEE Signal Processing Magazine, vol. 22, no. 2, pp. 2–2, 2005
  5. Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 8, pp. 1568–1579, 2005
  6. Maximum likelihood multiple-source localization using acoustic energy measurements with wireless sensor networks
    IEEE Transactions on Signal Processing, vol. 53, no. 1, pp. 44–53, 2005
  7. A Memory-Efficient and High-Speed Sine/Cosine Generator Based on Parallel CORDIC Rotations
    IEEE Signal Processing Letters, vol. 11, no. 2, pp. 152–155, 2004
  8. Vehicle classification in distributed sensor networks*1
    Journal of Parallel and Distributed Computing, vol. 64, no. 7, pp. 826–838, 2004
  9. Distance-Based Decision Fusion in a Distributed Wireless Sensor Network
    Telecommunication Systems, vol. 26, no. 2-4, pp. 339–350, 2004
  10. The Journal of Supercomputing, vol. 24, no. 3, pp. 229–249, 2003
  11. Editorial
    EURASIP Journal on Applied Signal Processing, vol. 2003, no. 4, pp. 319–320, 2003
  12. Energy-Based Collaborative Source Localization Using Acoustic Microsensor Array
    EURASIP Journal on Applied Signal Processing, vol. 2003, no. 4, pp. 321–337, 2003
  13. Mapping deep nested do-loop dsp algorithms to large scale FPGA array structures
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 2, pp. 208–217, 2003
  14. Editorial
    EURASIP Journal on Applied Signal Processing, vol. 2002, no. 9, pp. 877–878, 2002
  15. The Journal of VLSI Signal Processing, vol. 31, no. 1, pp. 5–5, 2002
  16. Detection, classification, and tracking of targets
    IEEE Signal Processing Magazine, vol. 19, no. 2, pp. 17–29, 2002
  17. Frame-level pipelined motion estimation array processor
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 2, pp. 248–251, 2001
  18. Maximum-likelihood parameter estimation for image ringing-artifact removal
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 8, pp. 963–973, 2001
  19. Efficient Implementation of Nested-Loop Multimedia Algorithms
    EURASIP Journal on Applied Signal Processing, vol. 2001, no. 3, pp. 129–146, 2001
  20. Adaptive wavelet packet based image coding with optimal entropy-constrained lattice vector quantizer (ECLVQ)
    IEEE Transactions on Signal Processing, vol. 46, no. 7, pp. 2019–2026, 1998
  21. Wavelet-based image coder with entropy-constrained lattice vector quantizer (ECLVQ)
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 8, pp. 1015–1030, 1998
  22. A modular high-throughput architecture for logarithmic search block-matching motion estimation
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 3, pp. 299–315, 1998
  23. A patient-adaptable ECG beat classifier using a mixture of experts approach
    IEEE Transactions on Biomedical Engineering, vol. 44, no. 9, pp. 891–900, 1997
  24. From Pattern Classification to Active Learning
    IEEE Signal Processing Magazine, vol. 14, no. 6, pp. 39–43, 1997
  25. A novel implementation of CORDIC algorithm using backward angle recoding (BAR)
    IEEE Transactions on Computers, vol. 45, no. 12, pp. 1370–1378, 1996
  26. On-line learning for active pattern recognition
    IEEE Signal Processing Letters, vol. 3, no. 11, pp. 301–303, 1996
  27. Multiprocessor implementation of real-time DSP algorithms
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, no. 3, pp. 393–403, 1995
  28. An efficient CORDIC array structure for the implementation of discrete cosine transform
    IEEE Transactions on Signal Processing, vol. 43, no. 1, pp. 331–336, 1995
  29. A novel modular systolic array architecture for full-search block matching motion estimation
    IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 5, pp. 407–416, 1995
  30. A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays
    Journal of VLSI Signal Processing, vol. 11, no. 1-2, pp. 133–150, 1995
  31. Fast pipelined CORDIC-based adaptive lattice predictor: algorithms and architecture
    IEE Proceedings - Vision, Image, and Signal Processing, vol. 142, no. 5, p. 339, 1995
  32. ARTIFICIAL INTELLIGENCE IN SCHEDULING AND INSTRUCTION SELECTION FOR DIGITAL SIGNAL PROCESSORS
    Applied Artificial Intelligence, vol. 8, no. 3, pp. 377–392, 1994
  33. Efficient scheduling and instruction selection for programmable digital signal processors
    IEEE Transactions on Signal Processing, vol. 42, no. 12, pp. 3549–3552, 1994
  34. Rate optimal scheduling of recursive DSP algorithms by unfolding
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 41, no. 10, pp. 672–675, 1994
  35. SEGMA: A Simulated Evolution Gate-Matrix Layout Algorithm
    VLSI Design, vol. 2, no. 3, pp. 241–257, 1994
  36. A fast pipelined VLSI adder for fast trigger decisions at the Superconducting Super Collider
    Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 330, no. 3, pp. 475–481, 1993
  37. PYFS-a statistical optimization method for integrated circuit yield enhancement
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 2, pp. 296–309, 1993
  38. SaPOSM: an optimization method applied to parameter extraction of MOSFET models
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 10, pp. 1481–1487, 1993
  39. An angle recording method for CORDIC algorithm implementation
    IEEE Transactions on Computers, vol. 42, no. 1, pp. 99–102, 1993
  40. MSSM?A design aid for multi-stage systolic mapping
    Journal of VLSI Signal Processing, vol. 4, no. 2-3, pp. 125–145, 1992
  41. CORDIC-based VLSI architectures for digital signal processing
    IEEE Signal Processing Magazine, vol. 9, no. 3, pp. 16–35, 1992
  42. The quantization effects of the CORDIC algorithm
    IEEE Transactions on Signal Processing, vol. 40, no. 4, pp. 834–844, 1992
  43. A novel implementation of a chirp Z-transform using a CORDIC processor
    IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 38, no. 2, pp. 352–354, 1990
  44. Frequency estimation error in Pisarenko harmonic decomposition method
    Proceedings of the IEEE, vol. 76, no. 1, pp. 82–84, 1988
  45. Paral lel VLSI Implementation of the Kalrman Filter
    IEEE Transactions on Aerospace and Electronic Systems, vol. AES-23, no. 2, pp. 215–224, 1987