Articles in Scholarly Journals [Incomplete List]

1. Effect of Improved Lower Bounds in Dynamic BDD Reordering
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 5, pp. 902–909, 2006
2. Testability of SPP Three-Level Logic Networks in Static Fault Models
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 2241–2248, 2006
3. Herd immunity conferred by killed oral cholera vaccines in Bangladesh: a reanalysis
   The Lancet, vol. 366, no. 9479, pp. 44–49, 2005
4. System level validation using formal techniques
   IEE Proceedings - Computers and Digital Techniques, vol. 152, no. 3, p. 393, 2005
5. Combining Ordered Best-First Search With Branch and Bound for Exact BDD Minimization
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 10, pp. 1515–1529, 2005
6. Synthesis of Fully Testable Circuits From BDDs
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 3, pp. 440–443, 2004
7. Using Word-Level Information in Formal Hardware Verification
   Automation and Remote Control, vol. 65, no. 6, pp. 963–977, 2004
8. Recursive bi-partitioning of netlists for large number of partitions
   Journal of Systems Architecture, vol. 49, no. 12-15, pp. 521–528, 2003
9. Exact routing with search space reduction
   IEEE Transactions on Computers, vol. 52, no. 6, pp. 815–825, 2003
10. Efficient minimization and manipulation of linearly transformed binary decision diagrams
    IEEE Transactions on Computers, vol. 52, no. 9, pp. 1196–1209, 2003
11. An improved branch and bound algorithm for exact bdd minimization
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 12, pp. 1657–1663, 2003
12. Minimization of free BDDs
    Integration, the VLSI Journal, vol. 32, no. 1-2, pp. 41–59, 2002
13. Verifying integrity of decision diagrams
    Integration, the VLSI Journal, vol. 32, no. 1-2, pp. 61–75, 2002
14. Minimization of Word-Level Decision Diagrams
    Integration, the VLSI Journal, vol. 33, no. 1-2, pp. 39–70, 2002
15. Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts
    VLSI Design, vol. 14, no. 1, pp. 35–52, 2002
16. Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs
    VLSI Design, vol. 14, no. 1, pp. 53–64, 2002
17. Journal of Electronic Testing, vol. 17, no. 1, pp. 37–51, 2001
18. Decision diagram method for calculation of pruned Walsh transform
    IEEE Transactions on Computers, vol. 50, no. 2, pp. 147–157, 2001
19. History-based dynamic BDD minimization
    Integration, the VLSI Journal, vol. 31, no. 1, pp. 51–63, 2001
20. Using lower bounds during dynamic BDD minimization
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, pp. 51–57, 2001
21. Fast exact minimization of BDD's
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 3, pp. 384–389, 2000
22. On the computational power of linearly transformed BDDs
    Information Processing Letters, vol. 75, no. 3, pp. 119–125, 2000
23. Boolean function representation and spectral characterization using AND/OR graphs
    Integration, the VLSI Journal, vol. 29, no. 2, pp. 101–116, 2000
24. EXOR transform of inputs to design efficient two-level AND/EXOR adders
    Electronics Letters, vol. 36, no. 3, p. 201, 2000
25. ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs
    Journal of Systems Architecture, vol. 46, no. 14, pp. 1321–1334, 2000
26. Pseudo-Kronecker expressions for symmetric functions
    IEEE Transactions on Computers, vol. 48, no. 9, pp. 987–990, 1999
27. Journal of Electronic Testing, vol. 14, no. 3, pp. 219–225, 1999
28. OKFDD minimization by genetic algorithms with application to circuit design
    Integration, the VLSI Journal, vol. 28, no. 2, pp. 121–139, 1999
29. BDD minimization using symmetries
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 2, pp. 81–100, 1999
30. The complexity of the inclusion operation on OFDD's
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 5, pp. 457–459, 1998
31. Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 10, pp. 965–973, 1998
32. On variable ordering and decomposition type choice in OKFDDs
    IEEE Transactions on Computers, vol. 47, no. 12, pp. 1398–1403, 1998
33. Symbolic simulation using decision diagrams
    Electronics Letters, vol. 33, no. 8, p. 665, 1997
34. Genetic algorithm for data sequencing
    Electronics Letters, vol. 33, no. 10, p. 843, 1997
35. Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 1, pp. 1–5, 1997
36. A genetic algorithm for RKRO minimization
    Expert Systems with Applications, vol. 12, no. 1, pp. 127–139, 1997
37. Formal Methods in System Design, vol. 11, no. 1, pp. 5–21, 1997
38. Relation between OFDDs and FPRMs
    Electronics Letters, vol. 32, no. 21, p. 1975, 1996
39. Fast OFDD-based minimization of fixed polarity Reed-Muller expressions
    IEEE Transactions on Computers, vol. 45, no. 11, pp. 1294–1299, 1996
40. On the generation of area-time optimal testable adders
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 9, pp. 1049–1066, 1995
41. On local transformations and path delay fault testability
    Journal of Electronic Testing, vol. 7, no. 3, pp. 173–191, 1995