Articles in Scholarly Journals [Incomplete List]

1. Formal verification of component-based designs
   Design Automation for Embedded Systems, vol. 11, no. 1, pp. 49–90, 2007
2. Fault-aware Communication Mapping for NoCs with Guaranteed Latency
   International Journal of Parallel Programming, vol. 35, no. 2, pp. 125–156, 2007
3. Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 3, pp. 262–275, 2007
4. Analysis and optimization of distributed real-time embedded systems
   ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 3, pp. 593–625, 2006
5. Power-aware test planning in the early system-on-chip design exploration process
   IEEE Transactions on Computers, vol. 55, no. 2, pp. 227–239, 2006
6. Quasi-Static Assignment of Voltages and Optional Cycles in Imprecise-Computation Systems With Energy Considerations
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 10, pp. 1117–1129, 2006
7. Test Time Minimization for Hybrid BIST of Core-Based Systems
   Journal of Computer Science and Technology, vol. 21, no. 6, pp. 907–912, 2006
8. Multiple-Constraint Driven System-on-Chip Test Time Optimization
   Journal of Electronic Testing, vol. 21, no. 6, pp. 599–611, 2005
9. Abort-on-Fail Based Test Scheduling
   Journal of Electronic Testing, vol. 21, no. 6, pp. 651–658, 2005
10. A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead
    Journal of Computer Science and Technology, vol. 20, no. 2, pp. 216–223, 2005
11. Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems
    IEE Proceedings - Computers and Digital Techniques, vol. 152, no. 1, p. 28, 2005
12. Analysis and optimisation of heterogeneous real-time embedded systems
    IEE Proceedings - Computers and Digital Techniques, vol. 152, no. 2, p. 130, 2005
13. Editorial: Emerging strategies for resource-constrained testing of system chips
    IEE Proceedings - Computers and Digital Techniques, vol. 152, no. 1, p. 65, 2005
14. Scheduling and Mapping in an IncrementalDesign Methodology for Distributed Real-Time Embedded Systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, pp. 793–811, 2004
15. Efficient Test Solutions for Core-Based Designs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 5, pp. 758–775, 2004
16. Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems
    Real-Time Systems, vol. 26, no. 3, pp. 297–325, 2004
17. Schedulability analysis and optimisation for the synthesis of multi-cluster distributed embedded systems
    IEE Proceedings - Computers and Digital Techniques, vol. 150, no. 5, p. 303, 2003
18. Modeling and formal verification of embedded systems based on a Petri net representation
    Journal of Systems Architecture, vol. 49, no. 12-15, pp. 571–598, 2003
19. Schedulability-driven frame packing for multi-cluster distributed embedded systems
    ACM SIGPLAN Notices, vol. 38, no. 7, p. 113, 2003
20. Journal of Electronic Testing, vol. 18, no. 4/5, pp. 385–400, 2002
21. Scheduling with bus access optimization for distributed embedded systems
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 5, pp. 472–491, 2000
22. An improved register–transfer level functional partitioning approach for testability
    Journal of Systems Architecture, vol. 46, no. 3, pp. 209–223, 2000
23. Journal of Electronic Testing, vol. 14, no. 1/2, pp. 103–113, 1999
24. Design Automation for Embedded Systems, vol. 2, no. 1, pp. 5–32, 1997
25. Post-synthesis back-annotation of timing information in behavioral VHDL
    Journal of Systems Architecture, vol. 42, no. 9-10, pp. 725–741, 1997
26. Inter-domain movement of functionality as a repartitioning strategy for hardware/software co-design
    Journal of Systems Architecture, vol. 43, no. 1-5, pp. 87–98, 1997
27. Synthesis of systems specified as interacting VHDL processes
    Integration, the VLSI Journal, vol. 21, no. 1-2, pp. 113–138, 1996
28. Automated transformation of algorithms into register-transfer level implementations
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 2, pp. 150–166, 1994
29. Digital system simulation with VHDL in a high-level synthesis system
    Microprocessing and Microprogramming, vol. 35, no. 1-5, pp. 263–269, 1992
30. An approach to testability analysis and improvement for VLSI systems
    Microprocessing and Microprogramming, vol. 35, no. 1-5, pp. 485–492, 1992
31. Testability measure with reconvergent fanout analysis and its applications
    Microprocessing and Microprogramming, vol. 32, no. 1-5, pp. 835–842, 1991
32. Let's design asynchronous VLSI systems
    Microprocessing and Microprogramming, vol. 24, no. 1-5, pp. 347–352, 1988
33. Parallelism extraction from sequential programs for VLSI applications
    Microprocessing and Microprogramming, vol. 23, no. 1-5, pp. 87–92, 1988