Table 6: List of terms.

Term Meaning

𝐸 𝑠 𝑝 𝑚 𝑟 Energy consumed during a reading from SPM.
𝐸 𝑠 𝑝 𝑚 𝑤 Energy consumed during a writing into SPM.
𝑁 𝑠 𝑝 𝑚 𝑟 Reading access number to SPM.
𝑁 𝑠 𝑝 𝑚 𝑤 Writing access number to SPM.
𝐸 𝑖 𝑐 𝑟 Energy consumed during a reading from instruction cache.
𝐸 𝑖 𝑐 𝑤 Energy consumed during a writing into instruction cache.
𝑁 𝑖 𝑐 𝑟 Reading access number to instruction cache.
𝑁 𝑖 𝑐 𝑤 Writing access number to instruction cache.
𝐸 𝑑 𝑟 𝑎 𝑚 𝑟 Energy consumed during a reading from DRAM.
𝐸 𝑑 𝑟 𝑎 𝑚 𝑤 Energy consumed during a writing into DRAM.
𝑁 𝑑 𝑟 𝑎 𝑚 𝑟 Reading access number to DRAM.
𝑁 𝑑 𝑟 𝑎 𝑚 𝑤 Writing access number to DRAM.
𝑊 𝑃 𝑖 The considered cache write policy: WT or WB. In case of WT, 𝑊 𝑃 𝑖 = 1 else in case of WB then 𝑊 𝑃 𝑖 = 0 .
𝐷 𝐵 𝑖 𝑘 Dirty Bit used in case of WB to indicate during the access 𝑘 if the instruction cache line has been modified before ( 𝐷 𝐵 𝑖 = 1 ) or not ( 𝐷 𝐵 𝑖 = 0 ) .
𝑖 𝑘 Type of the access 𝑘 to the instruction cache. In case of cache hit, 𝑖 𝑘 = 1 . In case of cache miss, 𝑖 𝑘 = 0 .