From Coherent States in Adjacent Graphene Layers toward Low-Power Logic Circuits

Figure 2

Circuit model of BiSFET used for SPICE simulation. 𝑉_𝑝−𝑉_𝑛 is the interlayer voltage, and 𝑉_𝐺,𝑝 and 𝑉_𝐺,𝑛 are the gate voltages. 𝐶_𝐺,𝑝, 𝐶_𝐺,𝑛, and 𝐶_𝑖𝑙 are parallel plate capacitances between the p-type graphene layer and its gate, between the n-type graphene layer and its gate, and between the n and p graphene layers, respectively. 𝐶_𝑄 are the quantum capacitances associated with the density of states of the individual graphene layers, and I is the interlayer current of all four applied voltages.